LoopAware/Replacement-TPM-2.0-module
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Replacement-TPM-2.0-module/tpm-module-14pin-spi-MZ32-A.../Revision A3/tpm-module-14pin-spi-RevA3/tpm-module-14pin-spi-RevA3....

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New branch for new revision
2024-03-12 11:46:53 +01:00
(kicad_pcb (version 20221018) (generator pcbnew)
(general
(thickness 1.6)
)
(paper "A4")
(layers
(0 "F.Cu" signal)
(31 "B.Cu" signal)
(32 "B.Adhes" user "B.Adhesive")
(33 "F.Adhes" user "F.Adhesive")
(34 "B.Paste" user)
(35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen")
(37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user)
(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user)
(45 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard")
(47 "F.CrtYd" user "F.Courtyard")
(48 "B.Fab" user)
(49 "F.Fab" user)
(50 "User.1" user)
(51 "User.2" user)
(52 "User.3" user)
(53 "User.4" user)
(54 "User.5" user)
(55 "User.6" user)
(56 "User.7" user)
(57 "User.8" user)
(58 "User.9" user)
)
(setup
(stackup
(layer "F.SilkS" (type "Top Silk Screen"))
(layer "F.Paste" (type "Top Solder Paste"))
(layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
(layer "F.Cu" (type "copper") (thickness 0.035))
(layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
(layer "B.Cu" (type "copper") (thickness 0.035))
(layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
(layer "B.Paste" (type "Bottom Solder Paste"))
(layer "B.SilkS" (type "Bottom Silk Screen"))
(layer "F.SilkS" (type "Top Silk Screen"))
(layer "F.Paste" (type "Top Solder Paste"))
(layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
(layer "F.Cu" (type "copper") (thickness 0.035))
(layer "dielectric 2" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
(layer "B.Cu" (type "copper") (thickness 0.035))
(layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
(layer "B.Paste" (type "Bottom Solder Paste"))
(layer "B.SilkS" (type "Bottom Silk Screen"))
(layer "F.SilkS" (type "Top Silk Screen"))
(layer "F.Paste" (type "Top Solder Paste"))
(layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
(layer "F.Cu" (type "copper") (thickness 0.035))
(layer "dielectric 3" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
(layer "B.Cu" (type "copper") (thickness 0.035))
(layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
(layer "B.Paste" (type "Bottom Solder Paste"))
(layer "B.SilkS" (type "Bottom Silk Screen"))
(copper_finish "None")
(dielectric_constraints no)
)
(pad_to_mask_clearance 0)
(pcbplotparams
(layerselection 0x00010fc_ffffffff)
(plot_on_all_layers_selection 0x0000000_00000000)
(disableapertmacros false)
(usegerberextensions false)
(usegerberattributes true)
(usegerberadvancedattributes true)
(creategerberjobfile true)
(dashed_line_dash_ratio 12.000000)
(dashed_line_gap_ratio 3.000000)
(svgprecision 6)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(dxfpolygonmode true)
(dxfimperialunits true)
(dxfusepcbnewfont true)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(sketchpadsonfab false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory "")
)
)
(net 0 "")
(net 1 "GND")
(net 2 "IRQ")
(net 3 "SPI_CLK")
(net 4 "SPI_MOSI")
(net 5 "SPI_MISO")
(net 6 "unconnected-(IC1-GPIO-Pad6)")
(net 7 "unconnected-(IC1-PP-Pad7)")
(net 8 "unconnected-(J1-Pin_4-Pad4)")
(net 9 "unconnected-(J1-Pin_8-Pad8)")
(net 10 "unconnected-(J1-Pin_9-Pad9)")
(net 11 "unconnected-(J1-Pin_10-Pad10)")
(net 12 "unconnected-(J1-Pin_11-Pad11)")
(net 13 "VDD")
(net 14 "RESET")
(net 15 "SPI_CS")
(footprint "Capacitor_SMD:C_0402_1005Metric" (layer "F.Cu")
(tstamp 0d48f3de-429a-44f6-87e8-8f0675772236)
(at 145.796 86.8452 90)
(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
(tags "capacitor")
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(property "Sheetfile" "tpm-module-14pin-spi-RevA3.kicad_sch")
New branch for new revision
2024-03-12 11:46:53 +01:00
(property "Sheetname" "")
(property "ki_description" "Unpolarized capacitor")
(property "ki_keywords" "cap capacitor")
(path "/02bd4d54-882e-439e-b1c2-88f37e7d09b2")
(attr smd)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(fp_text reference "C2" (at -0.0228 -1.1176 270) (layer "F.SilkS")
New branch for new revision
2024-03-12 11:46:53 +01:00
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 10c18a44-b217-46b0-8cf5-1f283b614254)
)
(fp_text value "100n" (at 0 1.16 90) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 9583b999-2641-4d2c-b435-f2103ed80d01)
)
(fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.Fab")
(effects (font (size 0.25 0.25) (thickness 0.04)))
(tstamp eec258c5-6fc7-4772-bc59-0249c5026f3d)
)
(fp_line (start -0.107836 -0.36) (end 0.107836 -0.36)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 718860a4-2370-4b08-894a-a61b022b77ca))
(fp_line (start -0.107836 0.36) (end 0.107836 0.36)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 1fea6ec3-1b11-4e76-9d98-3848cb73e87d))
(fp_line (start -0.91 -0.46) (end 0.91 -0.46)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 6727be5f-e0f0-450e-8a90-96241545fcbd))
(fp_line (start -0.91 0.46) (end -0.91 -0.46)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 21ab07ea-5e92-436f-8d00-1176b7381859))
(fp_line (start 0.91 -0.46) (end 0.91 0.46)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 6156e11a-8fc4-4e21-9bbd-93e8235729fc))
(fp_line (start 0.91 0.46) (end -0.91 0.46)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp f252f815-98e2-40e1-ae26-1cc8551313d6))
(fp_line (start -0.5 -0.25) (end 0.5 -0.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 27de7da1-433e-4de9-9313-9c069517127a))
(fp_line (start -0.5 0.25) (end -0.5 -0.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 71323e90-5a6a-421a-9dd1-5157bd1dfd57))
(fp_line (start 0.5 -0.25) (end 0.5 0.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp d3e7275b-c882-4920-8f20-d4a8e3e592d4))
(fp_line (start 0.5 0.25) (end -0.5 0.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 61bc4528-a99b-4cd6-8f10-94881abbbddc))
(pad "1" smd roundrect (at -0.48 0 90) (size 0.56 0.62) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 13 "VDD") (pintype "passive") (tstamp c1c6a7a9-b34f-4251-a2c4-95c09eb7c2fb))
(pad "2" smd roundrect (at 0.48 0 90) (size 0.56 0.62) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 1 "GND") (pintype "passive") (zone_connect 2) (tstamp 4647e9a0-baf1-4e6c-a1e1-8365d460a298))
(model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(footprint "Resistor_SMD:R_0402_1005Metric" (layer "F.Cu")
(tstamp 1769a4ee-56a4-4b21-a55b-38833d8b6900)
(at 144.7292 95.504)
(descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
(tags "resistor")
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(property "Sheetfile" "tpm-module-14pin-spi-RevA3.kicad_sch")
New branch for new revision
2024-03-12 11:46:53 +01:00
(property "Sheetname" "")
(property "ki_description" "Resistor")
(property "ki_keywords" "R res resistor")
(path "/c7fefcf9-ba90-436b-87c6-c31455c0a6e5")
(attr smd)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(fp_text reference "R2" (at -0.762 -1.0668) (layer "F.SilkS")
New branch for new revision
2024-03-12 11:46:53 +01:00
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 978fe13c-feb0-443e-b566-e71a9879ed0c)
)
(fp_text value "10k" (at 0 1.17) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 4d4b953f-a51e-4d7e-8bcf-56d8973a7909)
)
(fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
(effects (font (size 0.26 0.26) (thickness 0.04)))
(tstamp d1aa4591-0aad-49d2-b7e4-ac402bc2d269)
)
(fp_line (start -0.153641 -0.38) (end 0.153641 -0.38)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp ba54f68c-3a3c-454b-bf91-288eef7bdbb5))
(fp_line (start -0.153641 0.38) (end 0.153641 0.38)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp f4e7a9e3-af79-46b6-9fc2-2110038e913a))
(fp_line (start -0.93 -0.47) (end 0.93 -0.47)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp d65c1dbf-558b-4d05-9574-877f21142d4a))
(fp_line (start -0.93 0.47) (end -0.93 -0.47)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp fb23a4c9-9b8e-4c03-9f30-5134b7d9f874))
(fp_line (start 0.93 -0.47) (end 0.93 0.47)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp ce5ad14c-f178-4ebb-bff8-ad71849e120e))
(fp_line (start 0.93 0.47) (end -0.93 0.47)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp aea8d1ce-9c20-43e7-a301-d76897641262))
(fp_line (start -0.525 -0.27) (end 0.525 -0.27)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 2ebe2d68-b9e0-40c3-a9bb-ec5b3ca7f6e7))
(fp_line (start -0.525 0.27) (end -0.525 -0.27)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 10f73a82-efa7-4182-8c18-5203cbbb8a36))
(fp_line (start 0.525 -0.27) (end 0.525 0.27)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 71e22611-3472-4cfc-b46d-f8a0fceacc96))
(fp_line (start 0.525 0.27) (end -0.525 0.27)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 64a94a38-06be-4c83-9c72-91c2b50d3677))
(pad "1" smd roundrect (at -0.51 0) (size 0.54 0.64) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 13 "VDD") (pintype "passive") (tstamp 5642456e-136d-4324-94f6-e5084e15f21c))
(pad "2" smd roundrect (at 0.51 0) (size 0.54 0.64) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 2 "IRQ") (pintype "passive") (tstamp e2474ed4-956e-41fd-b29a-7fddc05c1123))
(model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(footprint "Connector_PinSocket_2.00mm:PinSocket_2x07_P2.00mm_Vertical_SMD" (layer "F.Cu")
New branch for new revision
2024-03-12 11:46:53 +01:00
(tstamp 53a533d2-704b-49aa-a740-67c21ceb6b4f)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(at 147.4575 101.931 90)
(descr "surface-mounted straight socket strip, 2x07, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated")
(tags "Surface mounted socket strip SMD 2x07 2.00mm double row")
(property "Sheetfile" "tpm-module-14pin-spi-RevA3.kicad_sch")
New branch for new revision
2024-03-12 11:46:53 +01:00
(property "Sheetname" "")
(property "ki_description" "Generic connector, double row, 02x07, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/)")
(property "ki_keywords" "connector")
(path "/7f7e32e8-e47e-41c2-adc4-ebdfb13f57e0")
(attr smd)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(fp_text reference "J1" (at 0 -8.5 90) (layer "F.SilkS")
New branch for new revision
2024-03-12 11:46:53 +01:00
(effects (font (size 1 1) (thickness 0.15)))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(tstamp e9cbc6c0-c345-4dd1-a977-319f16f2738c)
New branch for new revision
2024-03-12 11:46:53 +01:00
)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(fp_text value "79109-1006" (at 0 8.5 90) (layer "F.Fab")
New branch for new revision
2024-03-12 11:46:53 +01:00
(effects (font (size 1 1) (thickness 0.15)))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(tstamp 0fb0ab1c-ddef-44b2-a4bb-9e03a8285a16)
New branch for new revision
2024-03-12 11:46:53 +01:00
)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(fp_text user "${REFERENCE}" (at 0 0 180) (layer "F.Fab")
New branch for new revision
2024-03-12 11:46:53 +01:00
(effects (font (size 1 1) (thickness 0.15)))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(tstamp ae099ee3-09cd-47ad-b4b1-30fdf938f141)
)
(fp_line (start -2.06 -7.06) (end -2.06 -6.76)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp f7597439-0006-41b9-acb0-f336d63eb831))
(fp_line (start -2.06 -7.06) (end 2.06 -7.06)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 5870558a-618f-4037-bd3d-ca1bea4c96f1))
(fp_line (start -2.06 -5.24) (end -2.06 -4.76)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp a681db29-7899-4248-9b68-292641bef592))
(fp_line (start -2.06 -3.24) (end -2.06 -2.76)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 36e2627a-f322-45b0-992b-753ff4de823d))
(fp_line (start -2.06 -1.24) (end -2.06 -0.76)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 9c5b4837-246c-42a1-884c-7fc75c35ac74))
(fp_line (start -2.06 0.76) (end -2.06 1.24)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp da235a21-2a23-4fef-96e9-cf24927c3d6f))
(fp_line (start -2.06 2.76) (end -2.06 3.24)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 0c088cdc-6c77-4378-a2aa-58b99d4c474d))
(fp_line (start -2.06 4.76) (end -2.06 5.24)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 935bbafd-ce35-4ad5-b2f0-800ec93ce642))
(fp_line (start -2.06 6.76) (end -2.06 7.06)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp f14f0c6b-4a19-47da-8c88-1bfe2a72dcbb))
(fp_line (start -2.06 7.06) (end 2.06 7.06)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 8fe9c5b2-6da1-413e-815d-3a91098a7751))
(fp_line (start 2.06 -7.06) (end 2.06 -6.76)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp a7160077-9449-4b56-ac86-86331df7a497))
(fp_line (start 2.06 -6.76) (end 4.44 -6.76)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp f4814703-aff2-482a-a49f-11cbf4a0f416))
(fp_line (start 2.06 -5.24) (end 2.06 -4.76)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp ddce1996-5458-4282-a2a3-08edcc69dd68))
(fp_line (start 2.06 -3.24) (end 2.06 -2.76)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 969705ba-1913-42a3-af4c-fe2dd1074e42))
(fp_line (start 2.06 -1.24) (end 2.06 -0.76)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 038d8e60-95e5-4105-83af-f1864b6c2164))
(fp_line (start 2.06 0.76) (end 2.06 1.24)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp baa60ef6-3261-429e-a118-5ac71a3debf3))
(fp_line (start 2.06 2.76) (end 2.06 3.24)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 13c8db73-4781-4f11-a502-8080ac5e385a))
(fp_line (start 2.06 4.76) (end 2.06 5.24)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 2599341d-b757-46c4-a57c-1dbce35630bf))
(fp_line (start 2.06 6.76) (end 2.06 7.06)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp be524f2b-5cf0-4f24-8b9f-b0028bfe7f26))
(fp_line (start -5 -7.5) (end 5 -7.5)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp b5df305c-3f55-49fc-88f7-6829fe5d61ba))
(fp_line (start -5 7.5) (end -5 -7.5)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 1e28149b-fa85-43cc-83de-6dece29fb65c))
(fp_line (start 5 -7.5) (end 5 7.5)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 3c56eeae-46da-4429-a984-939a51d7df55))
(fp_line (start 5 7.5) (end -5 7.5)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp f4e35cff-633e-4df9-bdf8-e829d4b198e0))
(fp_line (start -3 -6.25) (end -2 -6.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 43d82b50-a9b9-401a-92b6-b3e4288d7ca2))
(fp_line (start -3 -5.75) (end -3 -6.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 956732fe-5650-4ccf-9e32-f577080511dc))
(fp_line (start -3 -4.25) (end -2 -4.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp c6dca6c9-a545-44ba-b841-f1a9e3dcdb50))
(fp_line (start -3 -3.75) (end -3 -4.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 1f0d7c9c-34f1-4f74-a935-0d7408a91ece))
(fp_line (start -3 -2.25) (end -2 -2.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 89a90e15-8d86-438c-b7d3-43dfcc2b31ff))
(fp_line (start -3 -1.75) (end -3 -2.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 9bc2f24e-3f0a-420c-a337-167fd0a46528))
(fp_line (start -3 -0.25) (end -2 -0.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 141c9b9f-2817-490e-92bc-694883fa52f3))
(fp_line (start -3 0.25) (end -3 -0.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 254065a2-976b-45d7-a800-e6f32178c56c))
(fp_line (start -3 1.75) (end -2 1.75)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 02263114-3a16-4832-b0a1-a940a8540657))
(fp_line (start -3 2.25) (end -3 1.75)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 906f4b26-445d-4718-a079-71e64fa4368c))
(fp_line (start -3 3.75) (end -2 3.75)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp dcd0a35e-8096-4e76-ad6b-b7a2e6dfc511))
(fp_line (start -3 4.25) (end -3 3.75)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 3ee7a301-d60c-4403-a8b6-157fcf9b852e))
(fp_line (start -3 5.75) (end -2 5.75)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 82a27955-65fd-4ddb-bcf4-dbe663872fb9))
(fp_line (start -3 6.25) (end -3 5.75)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp e6f9ea52-6296-4771-8675-c3281815a6b8))
(fp_line (start -2 -7) (end 1 -7)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp d0f9d8ee-9dc2-477b-aa82-05cef276594f))
(fp_line (start -2 -5.75) (end -3 -5.75)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp e17bcce3-a6bb-4fb0-91c8-257e37d28a12))
(fp_line (start -2 -3.75) (end -3 -3.75)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 5bada454-b8cb-4e7c-bd58-0834c11415fe))
(fp_line (start -2 -1.75) (end -3 -1.75)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 090d5925-fb6c-4d32-8922-48adedcdafe8))
(fp_line (start -2 0.25) (end -3 0.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp e6410e9c-4d4c-4fec-a1fc-05a8e2b7e4e3))
(fp_line (start -2 2.25) (end -3 2.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp e39f2b96-7ea0-490b-8264-ad353b941c29))
(fp_line (start -2 4.25) (end -3 4.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 98935f88-2806-4733-a8f5-f71884debdf3))
(fp_line (start -2 6.25) (end -3 6.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp dc4544af-8161-4293-a236-664d3400e6c8))
(fp_line (start -2 7) (end -2 -7)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp c241a989-2476-4255-a7c6-3d3e0ea8d688))
(fp_line (start 1 -7) (end 2 -6)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 423163e3-d16b-487b-b606-bd2af882839d))
(fp_line (start 2 -6.25) (end 3 -6.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 190e38fe-d1ea-4b29-96de-d2f4188595fd))
(fp_line (start 2 -6) (end 2 7)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp a8d42f62-9ba7-4354-8da2-9197e9ef33e6))
(fp_line (start 2 -4.25) (end 3 -4.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp d22d4c90-cb6e-4e58-b370-6b8c972aa3e7))
(fp_line (start 2 -2.25) (end 3 -2.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 463a6fcf-aa2c-4002-bc60-b8e3e27adf30))
(fp_line (start 2 -0.25) (end 3 -0.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 9f8eaaed-7924-48e4-8f3e-3f3ac697f876))
(fp_line (start 2 1.75) (end 3 1.75)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp e4f7185c-0667-4c9a-b01b-aa9fb9c0a49b))
(fp_line (start 2 3.75) (end 3 3.75)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp d7663c3a-4e31-4dc0-85c5-31c284683b29))
(fp_line (start 2 5.75) (end 3 5.75)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 709e5446-200c-4416-8f39-3b6858a21060))
(fp_line (start 2 7) (end -2 7)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp e959a10c-5e86-401e-bfa6-d523b4705707))
(fp_line (start 3 -6.25) (end 3 -5.75)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp ff61d9fc-59ee-4f19-8782-4a527632bae5))
(fp_line (start 3 -5.75) (end 2 -5.75)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp efdf1dfe-3def-4aca-a3e8-4d9253ee2abb))
(fp_line (start 3 -4.25) (end 3 -3.75)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp b009dab6-ba38-4cae-b4b0-fdee52a54bce))
(fp_line (start 3 -3.75) (end 2 -3.75)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp a952bdbf-ab66-4007-b9a2-977b088efcfb))
(fp_line (start 3 -2.25) (end 3 -1.75)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 461abff0-b4bd-4008-8be8-314a54f8c717))
(fp_line (start 3 -1.75) (end 2 -1.75)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 34b678fa-3bc3-4f90-b64d-ca1c90c752b3))
(fp_line (start 3 -0.25) (end 3 0.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 34c10622-247f-4a0f-b0c0-8198ac73628c))
(fp_line (start 3 0.25) (end 2 0.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 65816f00-3834-46ea-8ea7-f5d95fd1af29))
(fp_line (start 3 1.75) (end 3 2.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp d9f9a245-a67b-4078-89c5-98ef96ebca20))
(fp_line (start 3 2.25) (end 2 2.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 0b567cdd-9b40-4331-8dbd-0f3f6c19c0b1))
(fp_line (start 3 3.75) (end 3 4.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 06b00476-f7a4-4e96-ab96-9563762430c0))
(fp_line (start 3 4.25) (end 2 4.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp d093b443-59bf-4a1d-9b82-562095dfed2f))
(fp_line (start 3 5.75) (end 3 6.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 8d4952e7-8bb8-4c0b-a48e-85c8a982cc15))
(fp_line (start 3 6.25) (end 2 6.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp e427d774-e19f-47fb-883d-1ad5d71db1c0))
(pad "1" smd rect (at 3.125 -6 90) (size 2.75 1) (layers "F.Cu" "F.Paste" "F.Mask")
(net 3 "SPI_CLK") (pinfunction "Pin_1") (pintype "passive") (tstamp 7f807f6b-c265-4135-9d6f-60fd2309b65f))
(pad "2" smd rect (at -3.125 -6 90) (size 2.75 1) (layers "F.Cu" "F.Paste" "F.Mask")
(net 13 "VDD") (pinfunction "Pin_2") (pintype "passive") (tstamp a35acac7-cc6f-4c19-8298-c87e6343293c))
(pad "3" smd rect (at 3.125 -4 90) (size 2.75 1) (layers "F.Cu" "F.Paste" "F.Mask")
(net 14 "RESET") (pinfunction "Pin_3") (pintype "passive") (tstamp 3bf80e5e-b167-4b91-9dc8-6e064b8b90db))
(pad "4" smd rect (at -3.125 -4 90) (size 2.75 1) (layers "F.Cu" "F.Paste" "F.Mask")
(net 8 "unconnected-(J1-Pin_4-Pad4)") (pinfunction "Pin_4") (pintype "passive+no_connect") (tstamp d674a8a2-ee7f-4d59-bc5b-ae6a1d4f64ec))
(pad "5" smd rect (at 3.125 -2 90) (size 2.75 1) (layers "F.Cu" "F.Paste" "F.Mask")
(net 5 "SPI_MISO") (pinfunction "Pin_5") (pintype "passive") (tstamp cb85fcc5-8c2a-49f3-8022-55958eea9bfc))
(pad "6" smd rect (at -3.125 -2 90) (size 2.75 1) (layers "F.Cu" "F.Paste" "F.Mask")
(net 2 "IRQ") (pinfunction "Pin_6") (pintype "passive") (tstamp 95cf439c-1eed-42a1-ad60-463607d0ccf4))
(pad "7" smd rect (at 3.125 0 90) (size 2.75 1) (layers "F.Cu" "F.Paste" "F.Mask")
(net 4 "SPI_MOSI") (pinfunction "Pin_7") (pintype "passive") (tstamp 4f23a2bf-52be-4eb2-8add-f8a1bf86e2cb))
(pad "8" smd rect (at -3.125 0 90) (size 2.75 1) (layers "F.Cu" "F.Paste" "F.Mask")
(net 9 "unconnected-(J1-Pin_8-Pad8)") (pinfunction "Pin_8") (pintype "passive+no_connect") (tstamp 7d04ba2a-0600-4e49-bd1f-798355b2ec95))
(pad "9" smd rect (at 3.125 2 90) (size 2.75 1) (layers "F.Cu" "F.Paste" "F.Mask")
(net 10 "unconnected-(J1-Pin_9-Pad9)") (pinfunction "Pin_9") (pintype "passive+no_connect") (tstamp b07cb9ca-b7c1-425d-be1b-541ddb520f6f))
(pad "10" smd rect (at -3.125 2 90) (size 2.75 1) (layers "F.Cu" "F.Paste" "F.Mask")
(net 11 "unconnected-(J1-Pin_10-Pad10)") (pinfunction "Pin_10") (pintype "passive+no_connect") (tstamp c1560af4-a593-4f4a-8ab8-88a4b279e956))
(pad "11" smd rect (at 3.125 4 90) (size 2.75 1) (layers "F.Cu" "F.Paste" "F.Mask")
(net 12 "unconnected-(J1-Pin_11-Pad11)") (pinfunction "Pin_11") (pintype "passive+no_connect") (tstamp 4c88bff4-031e-4cb0-ad0c-88d2daf4546e))
(pad "12" smd rect (at -3.125 4 90) (size 2.75 1) (layers "F.Cu" "F.Paste" "F.Mask")
(net 1 "GND") (pinfunction "Pin_12") (pintype "passive") (zone_connect 2) (tstamp e0c32877-c750-46f1-bfbd-bb1b722a0cbf))
(pad "13" smd rect (at 3.125 6 90) (size 2.75 1) (layers "F.Cu" "F.Paste" "F.Mask")
(net 15 "SPI_CS") (pinfunction "Pin_13") (pintype "passive") (tstamp 8e895b63-1a6e-4426-9f34-9bddec1769c9))
(pad "14" smd rect (at -3.125 6 90) (size 2.75 1) (layers "F.Cu" "F.Paste" "F.Mask")
(net 1 "GND") (pinfunction "Pin_14") (pintype "passive") (zone_connect 2) (tstamp 434141cf-e171-46f7-889e-11ce8960223b))
(model "${KICAD6_3DMODEL_DIR}/Connector_PinSocket_2.00mm.3dshapes/PinSocket_2x07_P2.00mm_Vertical_SMD.wrl"
New branch for new revision
2024-03-12 11:46:53 +01:00
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(footprint "Capacitor_SMD:C_0402_1005Metric" (layer "F.Cu")
(tstamp 6255bcf8-fbea-4f31-bbf6-857ae5228f4b)
(at 149.9108 95.73 -90)
(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
(tags "capacitor")
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(property "Sheetfile" "tpm-module-14pin-spi-RevA3.kicad_sch")
New branch for new revision
2024-03-12 11:46:53 +01:00
(property "Sheetname" "")
(property "ki_description" "Unpolarized capacitor")
(property "ki_keywords" "cap capacitor")
(path "/af85213b-cf47-4ab2-b231-2180cae1c450")
(attr smd)
(fp_text reference "C3" (at 0.028 1.0668 90) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 608018c9-2fde-486a-ada1-c97eebbafeb3)
)
(fp_text value "100n" (at 0 1.16 90) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 3ba97e5a-ebe7-458f-81fb-4d278066ce1d)
)
(fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.Fab")
(effects (font (size 0.25 0.25) (thickness 0.04)))
(tstamp 28ef2aad-c541-4d2e-b13c-d5c31599db6d)
)
(fp_line (start -0.107836 -0.36) (end 0.107836 -0.36)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 86c9fa0b-2602-4343-b240-6612121a55d6))
(fp_line (start -0.107836 0.36) (end 0.107836 0.36)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp f40e36bc-ef7b-4b43-b89f-a9964c71d2f5))
(fp_line (start -0.91 -0.46) (end 0.91 -0.46)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 6b195c10-dced-4a82-b0a5-3ce969dd0a41))
(fp_line (start -0.91 0.46) (end -0.91 -0.46)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 3c89a61c-340a-43a1-8e8e-c8ab25ffb57a))
(fp_line (start 0.91 -0.46) (end 0.91 0.46)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 6c0803a5-fa96-4a05-973a-acac67cd45bc))
(fp_line (start 0.91 0.46) (end -0.91 0.46)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 3eed6f44-2111-4f21-a828-56b2fdc33a06))
(fp_line (start -0.5 -0.25) (end 0.5 -0.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 08e77bce-b9ca-4e8f-b7ea-6fc8e77b0e95))
(fp_line (start -0.5 0.25) (end -0.5 -0.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 5777366d-0c14-4e36-b059-6f8a26995306))
(fp_line (start 0.5 -0.25) (end 0.5 0.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 688fa9e6-23fb-4f27-a3a4-b2ff0d046fb8))
(fp_line (start 0.5 0.25) (end -0.5 0.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp c70437d7-53e2-4a4d-92c5-f963aac65ae7))
(pad "1" smd roundrect (at -0.48 0 270) (size 0.56 0.62) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 13 "VDD") (pintype "passive") (tstamp f282a7a3-34d2-43d2-8fdb-522e210d74f4))
(pad "2" smd roundrect (at 0.48 0 270) (size 0.56 0.62) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 1 "GND") (pintype "passive") (zone_connect 2) (tstamp 361340b1-a1d9-423e-902a-6120ebc1bbc4))
(model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(footprint "Capacitor_SMD:C_0402_1005Metric" (layer "F.Cu")
(tstamp 8e44dda0-681b-428c-9a6d-9a36173e1789)
(at 154.2288 91.0336)
(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
(tags "capacitor")
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(property "Sheetfile" "tpm-module-14pin-spi-RevA3.kicad_sch")
New branch for new revision
2024-03-12 11:46:53 +01:00
(property "Sheetname" "")
(property "ki_description" "Unpolarized capacitor")
(property "ki_keywords" "cap capacitor")
(path "/1ea9afa5-4d26-4a92-af54-01c5ef371380")
(attr smd)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(fp_text reference "C1" (at 0 -1.1684) (layer "F.SilkS")
New branch for new revision
2024-03-12 11:46:53 +01:00
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 46e169ab-4651-494b-8204-98b6c21f5a1d)
)
(fp_text value "1u" (at 0 1.16) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 85dd9820-cbc6-416d-9f8b-540d70dd7e1a)
)
(fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
(effects (font (size 0.25 0.25) (thickness 0.04)))
(tstamp 46ca481b-5bf0-4d9c-883a-23b9e5971b8a)
)
(fp_line (start -0.107836 -0.36) (end 0.107836 -0.36)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 1518351c-a8cd-4189-8f21-5e14aacfeba4))
(fp_line (start -0.107836 0.36) (end 0.107836 0.36)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 00e3fee1-7288-4540-bd0d-1111c717d19e))
(fp_line (start -0.91 -0.46) (end 0.91 -0.46)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 6bfa62b4-65b8-4543-a38d-a4e3ed0ee702))
(fp_line (start -0.91 0.46) (end -0.91 -0.46)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp d4b66de7-9d61-4f9e-89e6-de858fd9c785))
(fp_line (start 0.91 -0.46) (end 0.91 0.46)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 7e7e9d9b-554c-4e77-b537-402acf9a9499))
(fp_line (start 0.91 0.46) (end -0.91 0.46)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp da87faaf-a832-4e80-ae5c-0223d94c8558))
(fp_line (start -0.5 -0.25) (end 0.5 -0.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 4e884cd5-0030-4fc0-b1c8-f0df6bbc87be))
(fp_line (start -0.5 0.25) (end -0.5 -0.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 2650badb-b44a-47d3-8fc4-7b8918f1eedd))
(fp_line (start 0.5 -0.25) (end 0.5 0.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 043cbec8-5aa5-4f87-8a3a-7c169a1550db))
(fp_line (start 0.5 0.25) (end -0.5 0.25)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 4fbb5422-39be-4592-be46-47cd4cfddd12))
(pad "1" smd roundrect (at -0.48 0) (size 0.56 0.62) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 13 "VDD") (pintype "passive") (tstamp bd7e8952-825c-42c2-9c2e-1dd510736ceb))
(pad "2" smd roundrect (at 0.48 0) (size 0.56 0.62) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 1 "GND") (pintype "passive") (zone_connect 2) (tstamp ffc7c3d7-43dd-4ed5-a6f0-1baa4c8a4c36))
(model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(footprint "Resistor_SMD:R_0402_1005Metric" (layer "F.Cu")
(tstamp afe03d40-5939-478a-9467-e2bf8cce468f)
(at 142.3924 93.218 -90)
(descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
(tags "resistor")
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(property "Sheetfile" "tpm-module-14pin-spi-RevA3.kicad_sch")
New branch for new revision
2024-03-12 11:46:53 +01:00
(property "Sheetname" "")
(property "ki_description" "Resistor")
(property "ki_keywords" "R res resistor")
(path "/0f686736-c384-425e-914f-dc595efe9302")
(attr smd)
(fp_text reference "R3" (at 0 1.1684 90) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 696ee61b-15e4-4d05-b869-952c29039ac3)
)
(fp_text value "10k" (at 0 1.17 90) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 865e09cd-5363-44e3-89f7-1293894f5a03)
)
(fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.Fab")
(effects (font (size 0.26 0.26) (thickness 0.04)))
(tstamp 6cfcca61-c609-4c3d-bc45-5c2453eec3b9)
)
(fp_line (start -0.153641 -0.38) (end 0.153641 -0.38)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 37797a42-b52c-43e8-8801-84645b2f69c6))
(fp_line (start -0.153641 0.38) (end 0.153641 0.38)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 188deee2-5590-4d79-81ff-3eb955741d83))
(fp_line (start -0.93 -0.47) (end 0.93 -0.47)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 84c6e2c2-0ee6-455e-8dd3-e435deb889d1))
(fp_line (start -0.93 0.47) (end -0.93 -0.47)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 836bbf3d-4550-4c02-b206-2157ab087c9c))
(fp_line (start 0.93 -0.47) (end 0.93 0.47)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp f0cfd33b-ad3a-49c6-b000-b4a14c15bda1))
(fp_line (start 0.93 0.47) (end -0.93 0.47)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 0d7daac9-9d4d-4b6c-9c1e-2ea2940edec9))
(fp_line (start -0.525 -0.27) (end 0.525 -0.27)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp f4f48720-d000-44ef-b425-2c58fe5e3f53))
(fp_line (start -0.525 0.27) (end -0.525 -0.27)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 2d376afb-0db1-4fc0-b643-62cca5efd7da))
(fp_line (start 0.525 -0.27) (end 0.525 0.27)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp b0f6164f-554c-4196-a1a9-cd5468ba0be8))
(fp_line (start 0.525 0.27) (end -0.525 0.27)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 2df9745b-ee09-4f95-83cd-6b52daeed138))
(pad "1" smd roundrect (at -0.51 0 270) (size 0.54 0.64) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 13 "VDD") (pintype "passive") (tstamp 2dd003fb-2416-4c6a-8355-38e6102e6ffd))
(pad "2" smd roundrect (at 0.51 0 270) (size 0.54 0.64) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 14 "RESET") (pintype "passive") (tstamp ed52239f-e0b6-4060-b87d-fda33dc96ea5))
(model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(footprint "Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm" (layer "F.Cu")
(tstamp cdf9d416-3c43-418b-9677-0b59cb373d00)
(at 147.56 91.313 -90)
(descr "QFN, 32 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/8008S.pdf#page=20), generated with kicad-footprint-generator ipc_noLead_generator.py")
(tags "QFN NoLead")
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(property "Sheetfile" "tpm-module-14pin-spi-RevA3.kicad_sch")
New branch for new revision
2024-03-12 11:46:53 +01:00
(property "Sheetname" "")
(path "/41d51542-cb1d-4b70-a974-67a29a1b4ac7")
(attr smd)
(fp_text reference "IC1" (at -3.782 0.1025 -180) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 26590855-a0fb-4c43-b433-0169d3abbd5e)
)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(fp_text value "SLB 9670XQ2.0 FW7.85" (at 1.6002 10.7048 90) (layer "F.Fab")
New branch for new revision
2024-03-12 11:46:53 +01:00
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 48f174ae-69f0-4fd8-a1e0-914ce9137905)
)
(fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 40c9f9fa-0c38-41b6-b7e7-9e96f69f63a1)
)
(fp_line (start -2.61 -2.135) (end -2.61 -2.37)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 5f73a972-de57-4c53-a21a-6c0c65be02b3))
(fp_line (start -2.61 2.61) (end -2.61 2.135)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 54da7a26-4cb6-405f-9173-dcda58c8e031))
(fp_line (start -2.135 -2.61) (end -2.31 -2.61)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 35da8303-aca2-4ef5-9748-30d0dbdfcb1d))
(fp_line (start -2.135 2.61) (end -2.61 2.61)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp df47b68c-c382-4a39-92f0-ea397fe5ffab))
(fp_line (start 2.135 -2.61) (end 2.61 -2.61)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp d94c9232-7d5d-4685-9929-8cb76d156824))
(fp_line (start 2.135 2.61) (end 2.61 2.61)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 1751ddce-72d0-4a05-9767-a80bafabbb62))
(fp_line (start 2.61 -2.61) (end 2.61 -2.135)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 165720e9-eb5c-4828-84c9-3599705a27ec))
(fp_line (start 2.61 2.61) (end 2.61 2.135)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp de6919a4-b66f-493f-b6c4-402a366e142a))
(fp_poly
(pts
(xy -2.61 -2.61)
(xy -2.85 -2.94)
(xy -2.37 -2.94)
(xy -2.61 -2.61)
)
(stroke (width 0.12) (type solid)) (fill solid) (layer "F.SilkS") (tstamp cc4284c7-1f41-42a1-a5af-195f201c1d5a))
(fp_line (start -3.13 -3.13) (end -3.13 3.13)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp c5c5480a-3b49-45de-a41f-f7b997a37c6d))
(fp_line (start -3.13 3.13) (end 3.13 3.13)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 3189c684-5b23-4fde-8079-e40eca5a80d3))
(fp_line (start 3.13 -3.13) (end -3.13 -3.13)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 22aabfea-53ea-40aa-a19e-2f843d055d38))
(fp_line (start 3.13 3.13) (end 3.13 -3.13)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 3122c3fd-6466-4705-a0e1-842b050df92b))
(fp_line (start -2.5 -1.5) (end -1.5 -2.5)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 7b57138f-826e-4400-b236-67ebc8eb9b19))
(fp_line (start -2.5 2.5) (end -2.5 -1.5)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp c9f54dd7-8041-4fe8-8f5f-a9041f76dba8))
(fp_line (start -1.5 -2.5) (end 2.5 -2.5)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp e8ac0f94-38cd-48ba-a54c-87db488e26ed))
(fp_line (start 2.5 -2.5) (end 2.5 2.5)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp aa15d4cb-b5f4-46d4-a31d-48040ba711ba))
(fp_line (start 2.5 2.5) (end -2.5 2.5)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp ed5a9467-de15-4bee-968d-e67516172ce4))
(pad "" smd roundrect (at -1.03 -1.03 270) (size 0.83 0.83) (layers "F.Paste") (roundrect_rratio 0.25)
(zone_connect 2) (tstamp 27cde4d5-653d-48c1-be14-50eea7da408d))
(pad "" smd roundrect (at -1.03 0 270) (size 0.83 0.83) (layers "F.Paste") (roundrect_rratio 0.25)
(zone_connect 2) (tstamp 404d803c-c26e-4872-b5fc-528bf24d4cda))
(pad "" smd roundrect (at -1.03 1.03 270) (size 0.83 0.83) (layers "F.Paste") (roundrect_rratio 0.25)
(zone_connect 2) (tstamp 6574dfc5-c348-48eb-a8fb-244e2ceda545))
(pad "" smd roundrect (at 0 -1.03 270) (size 0.83 0.83) (layers "F.Paste") (roundrect_rratio 0.25)
(zone_connect 2) (tstamp 36bcc07f-da4f-411a-bc07-04c87f00b1b6))
(pad "" smd roundrect (at 0 0 270) (size 0.83 0.83) (layers "F.Paste") (roundrect_rratio 0.25)
(zone_connect 2) (tstamp 7ec20e90-fbbd-43fc-bc5f-576b9811907f))
(pad "" smd roundrect (at 0 1.03 270) (size 0.83 0.83) (layers "F.Paste") (roundrect_rratio 0.25)
(zone_connect 2) (tstamp 13845112-202e-457b-b930-8e96025ab9f2))
(pad "" smd roundrect (at 1.03 -1.03 270) (size 0.83 0.83) (layers "F.Paste") (roundrect_rratio 0.25)
(zone_connect 2) (tstamp 41333f45-1acc-4f91-9492-a66427e9bee9))
(pad "" smd roundrect (at 1.03 0 270) (size 0.83 0.83) (layers "F.Paste") (roundrect_rratio 0.25)
(zone_connect 2) (tstamp 83a7554f-a78c-4a63-8d85-00406778224f))
(pad "" smd roundrect (at 1.03 1.03 270) (size 0.83 0.83) (layers "F.Paste") (roundrect_rratio 0.25)
(zone_connect 2) (tstamp f10791de-73c6-46e0-91f5-656c2dea2a9d))
(pad "1" smd roundrect (at -2.4375 -1.75 270) (size 0.875 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 13 "VDD") (pinfunction "VDD") (pintype "power_in") (tstamp a53853dd-b7d8-4dca-8195-632d419f7d2b))
(pad "2" smd roundrect (at -2.4375 -1.25 270) (size 0.875 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 1 "GND") (pinfunction "GND") (pintype "power_in") (zone_connect 2) (tstamp b76aa975-f01a-47e8-974c-d305202b580a))
(pad "3" smd roundrect (at -2.4375 -0.75 270) (size 0.875 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 07bdff6b-4ba8-41e2-a2b9-05a9d5934595))
(pad "4" smd roundrect (at -2.4375 -0.25 270) (size 0.875 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 90835324-5fed-4c3a-a49d-b7e52bf7b047))
(pad "5" smd roundrect (at -2.4375 0.25 270) (size 0.875 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 36bb594b-a4e9-421b-b69e-98243a2b5009))
(pad "6" smd roundrect (at -2.4375 0.75 270) (size 0.875 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 6 "unconnected-(IC1-GPIO-Pad6)") (pinfunction "GPIO") (pintype "bidirectional+no_connect") (tstamp 7d8f3598-25cf-465d-bdf6-227f8e160813))
(pad "7" smd roundrect (at -2.4375 1.25 270) (size 0.875 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 7 "unconnected-(IC1-PP-Pad7)") (pinfunction "PP") (pintype "input+no_connect") (tstamp 276e6218-7a3d-4000-bae0-66e6c9722fba))
(pad "8" smd roundrect (at -2.4375 1.75 270) (size 0.875 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 13 "VDD") (pinfunction "VDD") (pintype "power_in") (tstamp ad713e19-67c7-4e39-bf3f-3bf577f4037e))
(pad "9" smd roundrect (at -1.75 2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 1 "GND") (pinfunction "GND") (pintype "power_in") (zone_connect 2) (tstamp f7016d44-18b0-41c5-af18-d2a2b26f0314))
(pad "10" smd roundrect (at -1.25 2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 7c14961a-d59a-4bfa-8332-11148224b306))
(pad "11" smd roundrect (at -0.75 2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 6c8e8fd8-799f-4d6e-aeb7-7f6cc361262a))
(pad "12" smd roundrect (at -0.25 2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp e621b936-d1fb-44db-bcf7-a2874a24514e))
(pad "13" smd roundrect (at 0.25 2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 0cc1554c-2f0b-44ab-9da0-af2bbb984cf7))
(pad "14" smd roundrect (at 0.75 2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 13 "VDD") (pinfunction "VDD") (pintype "power_in") (tstamp 140d8f35-39ad-43d1-bbd7-ba7cb8d1bd7d))
(pad "15" smd roundrect (at 1.25 2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 149280a5-0306-4960-9fec-620f2255be39))
(pad "16" smd roundrect (at 1.75 2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 1 "GND") (pinfunction "GND") (pintype "power_in") (zone_connect 2) (tstamp b5a98f95-af36-4cc8-90e9-9734456e696f))
(pad "17" smd roundrect (at 2.4375 1.75 270) (size 0.875 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 14 "RESET") (pinfunction "RESET#") (pintype "input") (tstamp 0e6f7d03-418a-4625-828a-a6c4054704a5))
(pad "18" smd roundrect (at 2.4375 1.25 270) (size 0.875 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 2 "IRQ") (pinfunction "PIRQ#") (pintype "output") (tstamp ad225419-9b9a-4ed1-aba0-a5ad42bb5147))
(pad "19" smd roundrect (at 2.4375 0.75 270) (size 0.875 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 3 "SPI_CLK") (pinfunction "SCLK") (pintype "input") (tstamp 2815c574-58ce-4c5a-8ae6-e39a13fc0c7b))
(pad "20" smd roundrect (at 2.4375 0.25 270) (size 0.875 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 15 "SPI_CS") (pinfunction "TPM_CS#") (pintype "input") (tstamp c2df2271-6ae4-42eb-a52c-13ed99964ef5))
(pad "21" smd roundrect (at 2.4375 -0.25 270) (size 0.875 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 4 "SPI_MOSI") (pinfunction "MOSI") (pintype "input") (tstamp 5d65968b-6146-40f4-be14-93bafc8dbadc))
(pad "22" smd roundrect (at 2.4375 -0.75 270) (size 0.875 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 13 "VDD") (pinfunction "VDD") (pintype "power_in") (tstamp a41352aa-9d6c-4086-b85f-2e6d40fb7ffe))
(pad "23" smd roundrect (at 2.4375 -1.25 270) (size 0.875 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 1 "GND") (pinfunction "GND") (pintype "power_in") (zone_connect 2) (tstamp 47c3b389-eb3b-4002-8b58-f60c0bf5f5ca))
(pad "24" smd roundrect (at 2.4375 -1.75 270) (size 0.875 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 5 "SPI_MISO") (pinfunction "MISO") (pintype "output") (tstamp 5e009eb6-8762-4ee3-b9d2-54d5c991cfaa))
(pad "25" smd roundrect (at 1.75 -2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp e1b27ea4-deed-4a95-8fd5-4aa705eee923))
(pad "26" smd roundrect (at 1.25 -2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 9815e798-e94a-4c6b-b2b2-4947553ac2fc))
(pad "27" smd roundrect (at 0.75 -2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 6ea7b7d6-e1f7-4a69-9266-2084348add3a))
(pad "28" smd roundrect (at 0.25 -2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 275d2652-9109-43a6-94b4-5441eb95638a))
(pad "29" smd roundrect (at -0.25 -2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp e6a8ee3b-abe6-4413-8ede-ba854d88be35))
(pad "30" smd roundrect (at -0.75 -2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 72e30e39-0985-4568-98d3-bf106378704e))
(pad "31" smd roundrect (at -1.25 -2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 1006d333-5c0b-497a-974b-fd14bfdc4fe5))
(pad "32" smd roundrect (at -1.75 -2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 1 "GND") (pinfunction "GND") (pintype "power_in") (zone_connect 2) (tstamp 711aab4b-918b-47b8-8ad7-c24e42ad0e4e))
(pad "33" smd rect (at 0 0 270) (size 3.1 3.1) (property pad_prop_heatsink) (layers "F.Cu" "F.Mask")
(net 1 "GND") (pinfunction "GND") (pintype "power_in") (zone_connect 2) (tstamp af1e8727-c081-4420-82fa-1a97cfa5a763))
(model "${KICAD7_3DMODEL_DIR}/Package_DFN_QFN.3dshapes/QFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm.wrl"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(footprint "Resistor_SMD:R_0402_1005Metric" (layer "F.Cu")
(tstamp d4e75aa1-e94b-4df1-903f-889176863ae8)
(at 155.0924 95.25 -90)
(descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
(tags "resistor")
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(property "Sheetfile" "tpm-module-14pin-spi-RevA3.kicad_sch")
New branch for new revision
2024-03-12 11:46:53 +01:00
(property "Sheetname" "")
(property "ki_description" "Resistor")
(property "ki_keywords" "R res resistor")
(path "/65fbf09a-dd01-444a-b7c8-40da949ce9b7")
(attr smd)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(fp_text reference "R1" (at -0.0508 1.1176 90) (layer "F.SilkS")
New branch for new revision
2024-03-12 11:46:53 +01:00
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 5b8523eb-dc93-4dfe-be65-711cf2d55f2a)
)
(fp_text value "10k" (at 0 1.17 90) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 014ffb7f-f614-49fa-a8e7-5da8593fc912)
)
(fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.Fab")
(effects (font (size 0.26 0.26) (thickness 0.04)))
(tstamp 63c7e4e6-e74f-42ba-bcde-c3beecfac8d0)
)
(fp_line (start -0.153641 -0.38) (end 0.153641 -0.38)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp c4042c42-72fe-4525-bd5d-fe1fa8ee89c9))
(fp_line (start -0.153641 0.38) (end 0.153641 0.38)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp afacffc8-9a7f-462b-99c9-1f7d76b08afe))
(fp_line (start -0.93 -0.47) (end 0.93 -0.47)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 18941a1a-0f87-4366-8ae0-3ff55d14450e))
(fp_line (start -0.93 0.47) (end -0.93 -0.47)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 744661b3-d0c3-4181-817c-f15ed7d3f018))
(fp_line (start 0.93 -0.47) (end 0.93 0.47)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 02d49f55-62e7-4878-91c0-af7fa829f1b0))
(fp_line (start 0.93 0.47) (end -0.93 0.47)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 9ca6d6ab-2dd7-4b51-8483-16c63de4553e))
(fp_line (start -0.525 -0.27) (end 0.525 -0.27)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp d7d43f18-cf30-42db-b7d7-f6b1db85df27))
(fp_line (start -0.525 0.27) (end -0.525 -0.27)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp dcf7093a-ccb3-460d-a377-1f20d3971c4f))
(fp_line (start 0.525 -0.27) (end 0.525 0.27)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp b6dc6901-56c6-4dee-92ba-ed339f181028))
(fp_line (start 0.525 0.27) (end -0.525 0.27)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 5723d4d7-3d7f-4459-a615-3c7766045257))
(pad "1" smd roundrect (at -0.51 0 270) (size 0.54 0.64) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 13 "VDD") (pintype "passive") (tstamp 5f5316ee-4ffe-4854-a51c-ee40f2cddf77))
(pad "2" smd roundrect (at 0.51 0 270) (size 0.54 0.64) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 15 "SPI_CS") (pintype "passive") (tstamp a95727f7-37a1-4ce6-988a-e44b32f4c9a6))
(model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(gr_rect (start 141.638 87.8332) (end 150.495 93.7438)
(stroke (width 0.2) (type solid)) (fill solid) (layer "B.Mask") (tstamp 121bd39d-2136-4f49-9428-4ef18826e3b9))
(gr_rect (start 150.495 87.8332) (end 153.1798 92.0928)
(stroke (width 0.2) (type solid)) (fill solid) (layer "B.Mask") (tstamp 42ee7651-a21b-4fb5-abf8-ef722efeca7a))
(gr_rect (start 141.638 97.536) (end 153.2636 98.646)
(stroke (width 0.2) (type solid)) (fill solid) (layer "B.Mask") (tstamp 854d9fba-e20a-4171-be85-a275a50cb38b))
(gr_rect (start 152.5854 94.742) (end 153.2636 97.503)
(stroke (width 0.2) (type solid)) (fill solid) (layer "B.Mask") (tstamp b78c6a27-f53b-4e6c-b4ce-6c733bf4d81f))
(gr_rect (start 141.638 96.0882) (end 143.891 97.503)
(stroke (width 0.2) (type solid)) (fill solid) (layer "B.Mask") (tstamp e555e336-8e40-407b-ad0b-631d8e22573c))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(gr_rect (start 137.7079 83.947) (end 157.1498 108.2908)
New branch for new revision
2024-03-12 11:46:53 +01:00
(stroke (width 0.1) (type default)) (fill none) (layer "Edge.Cuts") (tstamp 03f55458-31de-47f0-adf3-0debc0a12b39))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(gr_text "LA-CTM010-R Rev.A3" (at 155.702 87.122) (layer "B.SilkS") (tstamp 8f9abfdb-79cc-4628-ac90-a4ddd8c3aa58)
New branch for new revision
2024-03-12 11:46:53 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify left bottom mirror))
)
(gr_text "LoopAware CTM010 \nReplacement Module" (at 147.193 105.41) (layer "B.SilkS") (tstamp de7ed673-bda4-4245-b857-e70c9c733eec)
(effects (font (size 1 1) (thickness 0.15)) (justify bottom mirror))
)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(gr_text "LA-CTM010-R" (at 147.2184 86.614) (layer "F.SilkS") (tstamp edd14152-2dbf-43fc-ae5f-238f8ac1f4e3)
(effects (font (size 0.8 0.8) (thickness 0.15)) (justify left bottom))
New branch for new revision
2024-03-12 11:46:53 +01:00
)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(gr_text "LoopAware" (at 140.0556 95.1484 90) (layer "F.SilkS") (tstamp f06f8343-a7a0-4479-97db-9af7a1b1fd13)
New branch for new revision
2024-03-12 11:46:53 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify left bottom))
)
(gr_text "UNTESTED - COMES WITH NO WARRANTIES OR PROMISES\nTHIS MIGHT KILL YOUR COMPUTER AND SET YOUR HOUSE\nON FIRE, YOU HAVE BEEN WARNED." (at 147.0765 75.96) (layer "Dwgs.User") (tstamp a6bc2dbc-777b-4f4f-9a5f-6b04f6bdbd30)
(effects (font (size 1 1) (thickness 0.15)))
)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 139.4714 105.537) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 08df0e97-cd68-4df3-a7c6-273707763312))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 147.574 91.2876) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 1) (tstamp 0ffef92d-0407-4f46-a2df-ecec26afd62d))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 156.5656 95.1992) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 10b50777-5c27-4edc-b101-e9a4df55f5c1))
(via (at 156.5656 96.3422) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 10e011ad-c390-4dfd-a982-05eb0395d9bf))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 149.733 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 1b0b17df-6dab-4008-a9fe-9333e5945266))
(via (at 148.59 92.3036) (size 1) (drill 0.4) (layers "F.Cu" "B.Cu") (net 1) (tstamp 1d4771a4-8821-4944-b979-33268f1dcdfd))
(via (at 144.018 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 1ddb4550-8046-44e1-89d1-726bd4f94400))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 138.2776 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 1de4b21e-7327-43b9-a844-1ceeab406131))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 152.6032 91.3892) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 2099cf62-9d6a-492c-873c-6e54824d1c8a))
(via (at 142.1384 88.5444) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 22036eb2-2a20-42bc-83bc-e34315eed58f))
(via (at 138.303 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 24dbf298-4aaf-4c85-9c19-f009d1b47597))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 153.162 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 24fce741-520b-45b1-84bf-316729053768))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 146.558 92.3036) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 1) (tstamp 2620b94a-bcd2-45fc-8fc7-e6b9ce8fdeb4))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 138.3284 91.821) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 2697c5c7-09a3-4ded-a329-b117d959cfcd))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 140.589 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 2c4d894b-ecc9-4cc8-b3ab-fb59b773056f))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 156.5656 105.4862) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 2f6d3d59-6b3c-4273-9131-c60ff341b690))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 146.558 90.2716) (size 1) (drill 0.4) (layers "F.Cu" "B.Cu") (net 1) (tstamp 2f9daf2e-333d-4116-9476-1ddff01e7b48))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 138.3284 92.964) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 33e21c97-a91b-4aa7-828d-99fd8645ac59))
(via (at 138.3284 99.822) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 35b67169-cddb-4ec7-a366-ec67074add52))
(via (at 138.3284 96.393) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 38bc7fef-431c-477a-9d90-faab293d0448))
(via (at 155.3972 104.3432) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 3992befb-f4ec-40f6-87cc-55002855c080))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 139.446 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 3db1dae6-1a22-41a7-9238-7f2f2d98b31d))
(via (at 145.161 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 3fd4b5a7-6812-4576-8d0d-951f9d904a3b))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 156.5656 92.9132) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 40e01510-490e-4629-91d3-a1110c9a6212))
(via (at 156.5656 103.2002) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 4100b76d-5405-4ad1-b177-92c89aa67f37))
(via (at 156.5656 88.3412) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 41140946-33dc-4efb-8126-b121771f954c))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 142.875 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 421f3aaf-a0b2-4f88-9d26-daed16159dab))
(via (at 141.732 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 433f90f4-c6ce-431c-82d0-177d5bddbc7f))
(via (at 148.59 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 436b5fce-da1b-4ce2-8d0e-2032d6a966e0))
(via (at 143.6624 92.9132) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 479df61c-87f3-4d2b-b3fe-6668a2c561c0))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 156.5656 91.7702) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 4b96baf5-5e8f-44f0-a410-788e33762322))
(via (at 138.3284 86.106) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 4e20cf14-c6de-4446-b689-4ec17f646cbc))
(via (at 145.161 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 5126d4ca-324c-4014-a351-b67f88699ae0))
(via (at 156.5656 89.4842) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 5164a61d-8dd8-4d27-932f-23d0af70272b))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 154.305 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 51aa3dc3-eef8-4410-9230-d4fdcc62d2b9))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 156.5656 100.9142) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 546a3685-ac10-42d8-922a-85f60944f9ea))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 156.591 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 563c1316-23ca-4899-8d6a-7e6874c35234))
(via (at 142.0876 90.424) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 57f57e30-5441-4ce7-824f-801e0592b85e))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 138.3284 105.537) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 5ec8cf1d-3ed9-412d-a279-9160252fdc57))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 146.304 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 608ba7dc-e7f5-4cd9-a9bc-cb9084f59d53))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 152.019 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 6358702f-ff1c-49ba-90c5-044a8b46600b))
(via (at 138.3284 97.536) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 636ab354-86ba-4033-93ac-ff3a31ddd433))
(via (at 156.5656 99.7712) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 6787631a-6cb2-4f20-b859-3c78fb672407))
(via (at 154.305 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 6dead5f2-5d5f-4578-881d-8ea17d91c296))
(via (at 155.3972 105.4862) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 6eb1dd7c-0c75-4d83-98ef-f9dead753e2b))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 143.7132 90.424) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 76630413-5b8d-4ba0-94d7-b54f6b19201d))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 140.589 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 7678049f-ebc7-4a03-a9f1-dcbf8a444262))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 151.2824 88.646) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 79f89881-2dbc-4cfa-a8ae-6e8be097867f))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 138.3284 98.679) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 807174f7-5b4a-4a28-9bfb-1fa309b33a49))
(via (at 138.3284 87.249) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 821e0569-a3cb-43b6-a970-4112f335a855))
(via (at 156.5656 104.3432) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 82b11adb-bf60-4458-86a9-39bb591460a4))
(via (at 156.5656 98.6282) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 841d8a5b-2e4a-4338-8727-d3b066493a3c))
(via (at 139.446 106.68) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 84cc33a1-e390-4996-86b3-5c032ff5a944))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 145.1864 94.5388) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 85482d54-83bb-4082-a6f6-df53d52dacec))
(via (at 152.019 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 892eb29f-590f-4bc6-b416-3c24c272f4ff))
(via (at 152.8572 95.1992) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 8c3ae359-764d-4b6c-94c1-1bd533fb6217))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 138.3284 89.535) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 8e608d58-7b86-4299-9430-14795bca7ea6))
(via (at 138.3284 102.108) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 91b7482e-a7fd-4236-adb2-5b7577634196))
(via (at 155.448 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 921f3552-10de-44bd-91c7-d81fd302aa82))
(via (at 156.5656 90.6272) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 9350a4ec-8e1a-4108-9dc0-c79b8b764706))
(via (at 147.447 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 9a38378f-213f-4335-8bbf-506692ad977c))
(via (at 139.446 98.679) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 9d031a16-e2e7-46f8-8919-d2bd2ed9cfed))
(via (at 148.59 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp a13e5d23-a305-4e03-9f42-dea2fa9e99c6))
(via (at 146.304 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp a3b2019b-b5fb-4923-8ff0-4bee71f406bf))
(via (at 155.3972 99.7712) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp a6a5f8dc-d787-4e1b-978b-cb4e864f3f01))
(via (at 142.875 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp a7d743a7-1f2a-416e-872a-b94d2fda6e30))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 153.162 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp a8701b18-e9a1-4716-96b1-8b813a4fc765))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 138.3284 88.392) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp ab9081c5-5d8d-4286-b593-3267563ecc5c))
(via (at 156.5656 102.0572) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp ac7ff8c2-db97-4afa-9e88-9d0a1038d51d))
(via (at 156.5656 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp b21246ad-3e1d-4893-b943-4fb7ba8f0218))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 148.59 90.2716) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 1) (tstamp b6b46ec9-b709-46ae-b21f-a249a40c0181))
(via (at 147.447 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp b6e6a536-a38d-4172-a56b-2f3adc5f6937))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 138.3284 103.251) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp ba1078f0-745d-4b31-baad-6dd2f5411789))
(via (at 156.5656 94.0562) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp ba85a622-af12-458f-acc0-6c17c8f22e46))
(via (at 139.446 99.822) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp bd1ff15d-ddb7-4048-8aad-a89981153e9b))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 150.876 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp c047dd05-d0ca-4ea7-8051-f520a2f156bd))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 155.3972 103.2002) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp c0e9d8b8-7747-4b8a-8da7-5c927f961956))
(via (at 144.018 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp c302b13d-adca-4fa4-9542-55f35e8b3e96))
(via (at 155.3972 102.0572) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp c51e199e-cea4-4a7d-8deb-37d0eec02814))
(via (at 141.732 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp c54b1d92-dffe-449d-b9a3-eb0e272d0a14))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 152.6032 88.646) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp cc0ad23f-d2e8-47c7-93b0-0c993734dfaa))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 139.446 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp cef28706-8fef-46d8-b528-501a293bc95c))
(via (at 156.5656 87.1982) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp d186da34-3d84-4604-a8ba-d220ba9bc735))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 155.448 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp d4a1cf22-4d39-475a-84a8-52ab367bdc4e))
(via (at 138.303 106.68) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp d60ce66f-e47e-4390-900e-3fc0bfe64489))
(via (at 151.2824 91.3892) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp dbc9d70b-a0bf-4fa3-8b28-af5f4e3d20ea))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 150.876 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp dc7369c4-5e24-46e2-b7db-d18f5c75e10e))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 156.591 106.68) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp dd5c1d6e-692a-4b37-ad6d-b9c488d8bf13))
(via (at 143.7132 88.5444) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp e896de63-c80a-4345-a348-b4c0fe9a44e9))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 149.733 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp ea0cd1a3-e275-4e07-8287-c565720f712c))
(via (at 138.3284 95.25) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp ece93924-7f53-4c7c-998b-b85e26b1da10))
(via (at 156.5656 97.4852) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp ed65f487-2210-45ca-ac3b-5bf8a71cbf49))
(via (at 155.3972 100.9142) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp eda6c925-e834-45bb-a27b-f3344cf4c505))
(via (at 155.3972 98.6282) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp eea66e52-b337-4ee8-820b-45ea2eca5cbc))
(via (at 143.2052 96.3168) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp f0cc3d66-5467-4ec6-90e9-6fadb40d7fe8))
(via (at 138.3284 104.394) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp f0d73bc4-def7-47df-a0f3-4aae30ab3b35))
(via (at 138.3284 90.678) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp f1ac3dd0-5aa3-4d3a-a49f-6a4c7f7251c9))
(via (at 138.3284 94.107) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp f6417ba5-2f09-45ac-8b0a-99fada60124a))
(via (at 155.4226 106.68) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp f9e5c473-4770-416c-b16f-9aea24b82bbd))
(via (at 138.3284 100.965) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp fc79c446-11e4-4552-9a2c-6ca79d7b03df))
(via (at 156.5656 86.0552) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp fcde5520-e403-4c09-9fa9-7a0a814f730b))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 145.2392 95.504) (end 145.647926 95.504) (width 0.25) (layer "F.Cu") (net 2) (tstamp 2e59c076-8de9-4aec-8233-33d06385b37f))
(segment (start 146.31 94.1175) (end 146.31 94.60474) (width 0.25) (layer "F.Cu") (net 2) (tstamp 34d4efda-f958-4c98-9511-f33cedc9e3c0))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 145.4575 104.612) (end 145.4575 101.9385) (width 0.25) (layer "F.Cu") (net 2) (tstamp 58670307-35c2-4bc7-a7ef-1506700034ae))
(segment (start 145.4575 101.9385) (end 146.4564 100.9396) (width 0.25) (layer "F.Cu") (net 2) (tstamp 7de98759-86c4-45b6-9ecc-9d55c633fb7d))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 145.647926 95.266815) (end 145.647926 95.504) (width 0.25) (layer "F.Cu") (net 2) (tstamp 96bb05fe-917b-4337-a0c2-1453733910aa))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 146.4564 100.9396) (end 146.4564 96.675899) (width 0.25) (layer "F.Cu") (net 2) (tstamp a3f72484-1442-44e9-b484-c5830eabb1d1))
(segment (start 146.4564 96.675899) (end 145.647926 95.867426) (width 0.25) (layer "F.Cu") (net 2) (tstamp ba45f0fd-1b5c-4a6d-b258-d8a5a1aa087b))
(segment (start 145.647926 95.867426) (end 145.647926 95.504) (width 0.25) (layer "F.Cu") (net 2) (tstamp d52fdf2a-6097-4e5e-af49-2758cab03a9e))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 146.31 94.60474) (end 145.647926 95.266815) (width 0.25) (layer "F.Cu") (net 2) (tstamp dd6710eb-1cd9-4469-8124-11bf75f5735d))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 140.5768 98.362) (end 139.8375 97.6227) (width 0.25) (layer "F.Cu") (net 3) (tstamp 064c1b4b-b13a-4a8d-909f-0b89e92a4e90))
(segment (start 141.4575 98.362) (end 140.5768 98.362) (width 0.25) (layer "F.Cu") (net 3) (tstamp 32dceb8b-a475-49d4-909b-5ea16efd058a))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 146.81 95.130046) (end 146.81 94.1175) (width 0.25) (layer "F.Cu") (net 3) (tstamp 64da7667-3087-4f67-8095-c4f9eaf1ef1f))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 139.8375 97.6227) (end 139.8375 96.026) (width 0.25) (layer "F.Cu") (net 3) (tstamp c44211ef-8a2a-4aa7-b28c-40c4ee7b240e))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 146.372926 95.56712) (end 146.81 95.130046) (width 0.25) (layer "F.Cu") (net 3) (tstamp e9628d51-10bd-4b05-9da9-196726a039b8))
(via (at 146.372926 95.56712) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 3) (tstamp 3e32fdcd-f6f0-4a66-bb57-eb7ecd62ccd9))
(via (at 139.8375 96.026) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 3) (tstamp b3a9e520-5b93-4fd8-ad10-d1e73233305b))
(segment (start 146.372926 95.56712) (end 146.323806 95.518) (width 0.25) (layer "B.Cu") (net 3) (tstamp a28037ad-7b98-4180-8d89-887741645a1f))
(segment (start 140.3455 95.518) (end 139.8375 96.026) (width 0.25) (layer "B.Cu") (net 3) (tstamp a7852601-ec93-4cf1-a24d-255f2f7ac69f))
(segment (start 146.323806 95.518) (end 140.3455 95.518) (width 0.25) (layer "B.Cu") (net 3) (tstamp d502eabc-0b08-44fd-9521-8211c8e19ac1))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 147.8788 101.346) (end 147.4575 100.9247) (width 0.25) (layer "F.Cu") (net 4) (tstamp 05d5c8d6-a8a0-4764-b5e7-eb9bc7590534))
(segment (start 148.082 101.346) (end 147.8788 101.346) (width 0.25) (layer "F.Cu") (net 4) (tstamp 40a1eae1-2c35-44e1-a9c5-0656dd10556d))
(segment (start 147.81 95.106187) (end 148.4376 95.733787) (width 0.25) (layer "F.Cu") (net 4) (tstamp 72627b42-5174-498a-868a-bbff9def55b4))
(segment (start 148.4376 95.733787) (end 148.4376 100.9904) (width 0.25) (layer "F.Cu") (net 4) (tstamp d210ca0d-e361-4cd3-875b-1b42bb8bd76f))
(segment (start 147.81 94.1175) (end 147.81 95.106187) (width 0.25) (layer "F.Cu") (net 4) (tstamp d4c6f222-c919-4961-9918-f0c8c15d4cb3))
(segment (start 148.4376 100.9904) (end 148.082 101.346) (width 0.25) (layer "F.Cu") (net 4) (tstamp e5716ada-37cd-4fc3-b496-971b0899b8dc))
(segment (start 147.4575 98.806) (end 147.4575 100.9247) (width 0.25) (layer "F.Cu") (net 4) (tstamp feee654c-613a-4d6a-a447-b9a25e26ad25))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 149.31 93.7505) (end 150.8007 93.7505) (width 0.25) (layer "F.Cu") (net 5) (tstamp 1294bea3-ba1f-4f81-ac68-a993d641b522))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 145.4575 98.362) (end 145.4575 97.074) (width 0.25) (layer "F.Cu") (net 5) (tstamp 5608c48d-f1bb-486a-9e44-aa2aafe81bcb))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 150.8007 93.7505) (end 151.638 92.9132) (width 0.25) (layer "F.Cu") (net 5) (tstamp 6603b8b8-9880-428f-9b2b-a63b97008354))
(segment (start 151.638 92.9132) (end 152.0952 92.9132) (width 0.25) (layer "F.Cu") (net 5) (tstamp d2a543ef-7523-4b76-92b6-2d246b7d39dd))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 145.4575 97.074) (end 144.9175 96.534) (width 0.25) (layer "F.Cu") (net 5) (tstamp ddf3f96c-decc-42d9-b5a4-e265ff2d472b))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 152.0952 92.9132) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 5) (tstamp 36193547-ceee-4e72-b6bd-984be421024d))
(via (at 144.9175 96.534) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 5) (tstamp c6e20a54-f06c-4e8f-ad7a-28a1b7ff31ac))
(segment (start 152.0952 96.1136) (end 151.6748 96.534) (width 0.25) (layer "B.Cu") (net 5) (tstamp 0e964c7b-2386-46a6-9288-e6e64330c774))
(segment (start 152.0952 92.9132) (end 152.0952 96.1136) (width 0.25) (layer "B.Cu") (net 5) (tstamp adc44460-edb0-4e24-a7be-c59b5210d502))
(segment (start 151.6748 96.534) (end 144.9175 96.534) (width 0.25) (layer "B.Cu") (net 5) (tstamp f75918fa-4d44-4d44-a4e6-681f48705bf1))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 141.4575 104.612) (end 140.6292 104.612) (width 0.4) (layer "F.Cu") (net 13) (tstamp 0903ccfc-96a4-43f2-a205-39a4a3861e4b))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 155.0924 94.1324) (end 155.0924 92.3518) (width 0.4) (layer "F.Cu") (net 13) (tstamp 19d8ec36-9dee-4f68-a8bf-4d2f13102da1))
(segment (start 140.7668 91.7448) (end 140.7668 88.5444) (width 0.4) (layer "F.Cu") (net 13) (tstamp 1acc58f6-5e78-47a4-ae1c-b2f7fda59d58))
(segment (start 139.8515 101.473) (end 139.8375 101.487) (width 0.25) (layer "F.Cu") (net 13) (tstamp 1da3d8d2-53d9-4a96-93e2-cd937fcef469))
(segment (start 142.3924 91.7448) (end 143.51 91.7448) (width 0.4) (layer "F.Cu") (net 13) (tstamp 1fbee52a-cd7f-472e-a64e-8b35b9ee2ab9))
(segment (start 154.3792 94.74) (end 155.0924 94.74) (width 0.3) (layer "F.Cu") (net 13) (tstamp 24aaccab-ddae-4635-aa00-31bd1372238e))
(segment (start 150.876 94.6912) (end 151.4856 94.6912) (width 0.3) (layer "F.Cu") (net 13) (tstamp 2a98603d-56ef-494f-b839-1fe5c06698cf))
(segment (start 139.8235 101.473) (end 139.8375 101.487) (width 0.25) (layer "F.Cu") (net 13) (tstamp 2c328e89-79d8-4628-a825-103b62d10936))
(segment (start 153.7488 91.0336) (end 153.7488 88.2676) (width 0.4) (layer "F.Cu") (net 13) (tstamp 39c98f59-b96a-4a10-b7ee-f4d4f2c95d68))
(segment (start 149.9108 95.25) (end 150.3172 95.25) (width 0.3) (layer "F.Cu") (net 13) (tstamp 3e13326d-9b07-4b7e-bffd-86256b15f18d))
(segment (start 145.81 88.8755) (end 145.81 87.39) (width 0.3) (layer "F.Cu") (net 13) (tstamp 4083fb30-947c-4478-8b51-b3b925e2c88d))
(segment (start 140.7668 91.7448) (end 142.3924 91.7448) (width 0.4) (layer "F.Cu") (net 13) (tstamp 47975418-336a-4d56-a75f-3cc57b6f092b))
(segment (start 145.796 87.3252) (end 149.3012 87.3252) (width 0.4) (layer "F.Cu") (net 13) (tstamp 4ef7dd4d-7799-49cc-85b7-d35d2ffe6ec4))
(segment (start 154.0256 94.3864) (end 154.3792 94.74) (width 0.3) (layer "F.Cu") (net 13) (tstamp 54dd122c-6118-44c8-b955-713dbfcbe435))
(segment (start 141.986 87.3252) (end 145.796 87.3252) (width 0.4) (layer "F.Cu") (net 13) (tstamp 56cc296e-3712-4128-b032-2a516017e038))
(segment (start 142.3924 92.708) (end 142.3924 91.7448) (width 0.4) (layer "F.Cu") (net 13) (tstamp 5cd8e5a2-28bb-4950-8c04-164e5333cf33))
(segment (start 151.7904 94.3864) (end 154.0256 94.3864) (width 0.3) (layer "F.Cu") (net 13) (tstamp 6aa54658-4632-4dae-8d14-3bbd975e8cfd))
(segment (start 140.7668 88.5444) (end 141.986 87.3252) (width 0.4) (layer "F.Cu") (net 13) (tstamp 6c420ed1-c024-43b9-a5eb-d9d8cdf19b04))
(segment (start 148.31 94.23774) (end 149.32226 95.25) (width 0.25) (layer "F.Cu") (net 13) (tstamp 72a54659-34e7-4d4b-a2da-dd6299d493e1))
(segment (start 143.8282 92.063) (end 145.1225 92.063) (width 0.25) (layer "F.Cu") (net 13) (tstamp 73109d04-b07c-4ae8-bf58-5b53a8b4eaaf))
(segment (start 143.8656 94.5896) (end 143.8656 95.1504) (width 0.25) (layer "F.Cu") (net 13) (tstamp 7b2d34cb-113b-445e-9d90-734974502711))
(segment (start 151.4856 94.6912) (end 151.7904 94.3864) (width 0.3) (layer "F.Cu") (net 13) (tstamp 7ebc9264-e61e-48b0-9928-8b5317e11d6b))
(segment (start 155.0924 94.74) (end 155.0924 94.1324) (width 0.4) (layer "F.Cu") (net 13) (tstamp 86c437bd-1e79-49fd-8619-a029fea31940))
(segment (start 149.3012 87.3252) (end 152.8064 87.3252) (width 0.4) (layer "F.Cu") (net 13) (tstamp 8e1d6dfb-779c-4cd0-b644-2e9bd7b95a59))
(segment (start 153.7742 92.0242) (end 153.7742 91.059) (width 0.4) (layer "F.Cu") (net 13) (tstamp a51d5fcc-caae-4712-8895-1e3e36107297))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 140.6292 104.612) (end 139.8375 103.8203) (width 0.4) (layer "F.Cu") (net 13) (tstamp ab514c3b-9e4c-4eba-8273-7271cf8ebbdb))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 149.32226 95.25) (end 149.9108 95.25) (width 0.25) (layer "F.Cu") (net 13) (tstamp b2bbb83b-cfd3-4376-90bb-56ad9cf3e1f8))
(segment (start 143.51 91.7448) (end 143.8282 92.063) (width 0.25) (layer "F.Cu") (net 13) (tstamp bd7ef63e-394a-4f91-95cc-f6c2d3a35d90))
(segment (start 149.31 88.8755) (end 149.31 87.334) (width 0.25) (layer "F.Cu") (net 13) (tstamp be38f4e8-ef61-429f-a714-0e727a9b53e1))
(segment (start 152.8064 87.3252) (end 153.7488 88.2676) (width 0.4) (layer "F.Cu") (net 13) (tstamp c07e72f9-54ca-49e2-bacf-9073b6bac702))
(segment (start 148.31 93.7505) (end 148.31 94.23774) (width 0.25) (layer "F.Cu") (net 13) (tstamp c07f5f52-cd13-4d62-9b56-93089fb67ed5))
(segment (start 154.7648 92.0242) (end 153.7742 92.0242) (width 0.4) (layer "F.Cu") (net 13) (tstamp c10f70c7-0334-4b37-8b18-0c0583785612))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 139.8375 103.8203) (end 139.8375 101.487) (width 0.4) (layer "F.Cu") (net 13) (tstamp c4577c96-68fc-42a1-9570-9e0407923c8b))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 143.8656 95.1504) (end 144.2192 95.504) (width 0.25) (layer "F.Cu") (net 13) (tstamp cbae47af-4887-48e4-95c7-332939c2c0c9))
(segment (start 153.7742 92.9386) (end 153.7742 92.0242) (width 0.4) (layer "F.Cu") (net 13) (tstamp e43f2464-2c37-4a8e-acf3-502234ab6cb3))
(segment (start 155.0924 92.3518) (end 154.7648 92.0242) (width 0.4) (layer "F.Cu") (net 13) (tstamp e97a64df-bd60-4788-831e-5a08d1bdc459))
(segment (start 150.3172 95.25) (end 150.876 94.6912) (width 0.3) (layer "F.Cu") (net 13) (tstamp f0db30d6-c20f-400f-806a-efdcba9e49c9))
(segment (start 145.81 89.2425) (end 145.81 88.533) (width 0.25) (layer "F.Cu") (net 13) (tstamp f2fdd02d-60f4-4943-ad08-ab1c1cc9d3a4))
(via (at 139.8375 101.487) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 13) (tstamp 989fd409-a9fc-46da-b3f8-d7648d9b5859))
(via (at 153.7742 92.9386) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 13) (tstamp a9a3da5f-0736-41ac-839b-969673b3ce17))
(via (at 140.7668 91.7448) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 13) (tstamp d13f8010-107c-418a-9ce3-b15d64ec7230))
(via (at 143.8656 94.5896) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 13) (tstamp fabefb4a-b29e-48f8-9e61-b592b2f0bf26))
(segment (start 140.7668 93.6244) (end 140.7668 91.7448) (width 0.4) (layer "B.Cu") (net 13) (tstamp 1af14add-a7f4-4caa-8aeb-c4c28fa4131c))
(segment (start 139.8375 101.487) (end 153.4265 101.487) (width 0.4) (layer "B.Cu") (net 13) (tstamp 4470c0ec-dd0c-4562-bd92-7c551dc688c1))
(segment (start 153.4265 101.487) (end 153.8075 101.106) (width 0.4) (layer "B.Cu") (net 13) (tstamp a0ec0a6f-7f4f-481a-a107-6c0573cf5200))
(segment (start 143.8656 94.5896) (end 141.732 94.5896) (width 0.4) (layer "B.Cu") (net 13) (tstamp b3048867-9b3b-45a0-81ef-1681e014bf48))
(segment (start 153.8075 101.106) (end 153.8075 92.9719) (width 0.4) (layer "B.Cu") (net 13) (tstamp d45e2231-657d-401f-92cc-39c15d30e931))
(segment (start 141.732 94.5896) (end 140.7668 93.6244) (width 0.4) (layer "B.Cu") (net 13) (tstamp e71988dc-694c-450b-879a-42df1c04558e))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 142.3924 93.728) (end 142.3924 97.2969) (width 0.25) (layer "F.Cu") (net 14) (tstamp 045371ec-edad-4d63-8b8f-40ed5e336bf3))
(segment (start 142.3924 97.2969) (end 143.4575 98.362) (width 0.25) (layer "F.Cu") (net 14) (tstamp 07bbcfe3-ac8d-4864-ba26-70995bdba010))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 145.81 93.7505) (end 142.4149 93.7505) (width 0.25) (layer "F.Cu") (net 14) (tstamp 672ba4e2-907b-4f91-aa0c-940560aa9cde))
(segment (start 154.0764 96.0628) (end 154.3792 95.76) (width 0.25) (layer "F.Cu") (net 15) (tstamp 0fde9e5a-781d-4cba-9702-d4d400a2d42d))
(segment (start 147.31 94.1175) (end 147.31 95.631492) (width 0.25) (layer "F.Cu") (net 15) (tstamp 2b07a606-1850-4c2c-88d2-e344f4d628c8))
(segment (start 155.0775 95.7749) (end 155.0924 95.76) (width 0.25) (layer "F.Cu") (net 15) (tstamp 42866959-c87e-4a43-847b-ffaf1fa99e67))
(segment (start 147.31 95.631492) (end 147.487508 95.809) (width 0.25) (layer "F.Cu") (net 15) (tstamp 6f7bae07-2595-459f-8495-ad3145404ee2))
(segment (start 151.328547 95.809) (end 151.377547 95.76) (width 0.25) (layer "F.Cu") (net 15) (tstamp 8d00b39b-6ec1-4f21-a98f-900d7d60d072))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 154.3172 98.362) (end 155.0924 97.5868) (width 0.25) (layer "F.Cu") (net 15) (tstamp acadb7f6-9c34-4546-92f0-01176976f6f2))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 154.3792 95.76) (end 155.0924 95.76) (width 0.25) (layer "F.Cu") (net 15) (tstamp bd2018f3-86ea-4333-a0b9-14b22289f22f))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 153.4575 98.362) (end 154.3172 98.362) (width 0.25) (layer "F.Cu") (net 15) (tstamp d6fcc18c-504e-4dd9-9233-244b0efe70ec))
(segment (start 155.0924 97.5868) (end 155.0924 95.76) (width 0.25) (layer "F.Cu") (net 15) (tstamp d83d7fcb-f0ef-42eb-97f6-1951a01b3eb4))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 151.582347 96.0628) (end 154.0764 96.0628) (width 0.25) (layer "F.Cu") (net 15) (tstamp eb3fd95a-31f6-4b59-9d7d-c7c78a9be90f))
(segment (start 151.328547 95.809) (end 151.582347 96.0628) (width 0.25) (layer "F.Cu") (net 15) (tstamp fc61e464-bb2b-476f-bfc1-d157cd7fe125))
(via (at 147.487508 95.809) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 15) (tstamp 20138616-1a75-489e-95db-a8ecb1a521b2))
(via (at 151.328547 95.809) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 15) (tstamp 22b8939d-7c9e-4dab-b0bd-bbc577d0c413))
(segment (start 147.487508 95.809) (end 151.328547 95.809) (width 0.25) (layer "B.Cu") (net 15) (tstamp ab2fecfc-1b54-49cd-b3a6-3514821fe977))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(zone (net 13) (net_name "VDD") (layer "F.Cu") (tstamp 063147a2-001f-4131-b5fc-f635db00d88c) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30008)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 141.5668 91.9448)
(xy 141.5668 91.5448)
(xy 140.919873 91.375248)
(xy 140.7658 91.7448)
(xy 140.919873 92.114352)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 141.558067 91.542511)
(xy 141.5652 91.547923)
(xy 141.5668 91.553828)
(xy 141.5668 91.935771)
(xy 141.563373 91.944044)
(xy 141.558066 91.947089)
(xy 140.92972 92.111771)
(xy 140.920849 92.110553)
(xy 140.915955 92.104955)
(xy 140.767675 91.749299)
(xy 140.767655 91.74035)
(xy 140.915956 91.384642)
(xy 140.922302 91.378326)
(xy 140.929717 91.377828)
)
)
)
(zone (net 13) (net_name "VDD") (layer "F.Cu") (tstamp 0de1dd3f-a791-4577-a257-3f3e70da811b) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30018)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 145.206 87.1252)
(xy 145.206 87.5252)
(xy 145.626 87.6052)
(xy 145.797 87.3252)
(xy 145.626 87.0452)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 145.626814 87.048533)
(xy 145.63022 87.05211)
(xy 145.793275 87.319102)
(xy 145.794663 87.327949)
(xy 145.793275 87.331298)
(xy 145.63022 87.598289)
(xy 145.622984 87.603564)
(xy 145.618046 87.603684)
(xy 145.215511 87.527011)
(xy 145.208025 87.522097)
(xy 145.206 87.515518)
(xy 145.206 87.134881)
(xy 145.209427 87.126608)
(xy 145.215509 87.123388)
(xy 145.618046 87.046715)
)
)
)
(zone (net 5) (net_name "SPI_MISO") (layer "F.Cu") (tstamp 0e97bd69-8a85-435e-a199-366a4b949daa) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30002)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 145.444773 96.884496)
(xy 145.267996 97.061273)
(xy 144.9575 97.431)
(xy 145.458207 98.806707)
(xy 145.882592 97.431)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 145.452082 96.893732)
(xy 145.452937 96.894686)
(xy 145.878446 97.425825)
(xy 145.878715 97.42616)
(xy 145.881213 97.434759)
(xy 145.880764 97.436924)
(xy 145.468471 98.773432)
(xy 145.462758 98.780327)
(xy 145.453842 98.781163)
(xy 145.446947 98.77545)
(xy 145.446297 98.773985)
(xy 145.446096 98.773432)
(xy 144.959811 97.437349)
(xy 144.960201 97.428404)
(xy 144.961841 97.425829)
(xy 145.267681 97.061647)
(xy 145.268345 97.060923)
(xy 145.435537 96.893731)
(xy 145.443809 96.890305)
)
)
)
(zone (net 13) (net_name "VDD") (layer "F.Cu") (tstamp 13ea8b08-2f1a-4335-a128-eb9742403ec3) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30024)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 155.2924 94.2)
(xy 154.8924 94.2)
(xy 154.8224 94.502552)
(xy 155.0924 94.741)
(xy 155.3624 94.502552)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 155.291371 94.203427)
(xy 155.294497 94.209063)
(xy 155.360828 94.495759)
(xy 155.359354 94.504591)
(xy 155.357174 94.507166)
(xy 155.100145 94.73416)
(xy 155.091675 94.737068)
(xy 155.084655 94.73416)
(xy 154.827625 94.507166)
(xy 154.823692 94.499121)
(xy 154.82397 94.495763)
(xy 154.890303 94.209062)
(xy 154.895507 94.201775)
(xy 154.901702 94.2)
(xy 155.283098 94.2)
)
)
)
(zone (net 13) (net_name "VDD") (layer "F.Cu") (tstamp 177176c5-4e0c-483a-84dc-a586ecf3023d) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30010)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 139.6375 102.287)
(xy 140.0375 102.287)
(xy 140.207052 101.640073)
(xy 139.8375 101.486)
(xy 139.467948 101.640073)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 140.197655 101.636155)
(xy 140.203973 101.642502)
(xy 140.204471 101.64992)
(xy 140.039789 102.278266)
(xy 140.034376 102.2854)
(xy 140.028471 102.287)
(xy 139.646529 102.287)
(xy 139.638256 102.283573)
(xy 139.635211 102.278266)
(xy 139.620085 102.220553)
(xy 139.470528 101.649918)
(xy 139.471746 101.641049)
(xy 139.477342 101.636156)
(xy 139.833 101.487875)
(xy 139.841949 101.487855)
)
)
)
(zone (net 13) (net_name "VDD") (layer "F.Cu") (tstamp 1c680b84-ed44-49b6-b865-b4c58d204110) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30020)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 153.9488 90.4436)
(xy 153.5488 90.4436)
(xy 153.4688 90.8636)
(xy 153.7488 91.0346)
(xy 154.0288 90.8636)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 153.947392 90.447027)
(xy 153.950612 90.453111)
(xy 154.027284 90.855646)
(xy 154.025466 90.864414)
(xy 154.021889 90.86782)
(xy 153.754898 91.030875)
(xy 153.746051 91.032263)
(xy 153.742702 91.030875)
(xy 153.47571 90.86782)
(xy 153.470435 90.860584)
(xy 153.470315 90.855646)
(xy 153.546988 90.453111)
(xy 153.551902 90.445625)
(xy 153.558481 90.4436)
(xy 153.939119 90.4436)
)
)
)
(zone (net 13) (net_name "VDD") (layer "F.Cu") (tstamp 2203bbef-a5b8-4cce-9ea1-8f65664b8999) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30004)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 140.649211 104.349169)
(xy 140.366369 104.632011)
(xy 140.9575 105.340439)
(xy 141.458207 105.056707)
(xy 140.9575 104.176481)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 140.963247 104.186584)
(xy 141.452412 105.04652)
(xy 141.453524 105.055406)
(xy 141.448027 105.062475)
(xy 141.44801 105.062484)
(xy 140.965995 105.335625)
(xy 140.957108 105.336723)
(xy 140.951244 105.332942)
(xy 140.725567 105.062484)
(xy 140.373217 104.640218)
(xy 140.370548 104.631672)
(xy 140.373927 104.624452)
(xy 140.648069 104.35031)
(xy 140.650616 104.348381)
(xy 140.94736 104.18216)
(xy 140.956252 104.181108)
)
)
)
(zone (net 13) (net_name "VDD") (layer "F.Cu") (tstamp 23120bd6-a4c6-4b44-8270-cedc8951ef77) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30023)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 142.5924 92.168)
(xy 142.1924 92.168)
(xy 142.1224 92.470552)
(xy 142.3924 92.709)
(xy 142.6624 92.470552)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 142.591371 92.171427)
(xy 142.594497 92.177063)
(xy 142.660828 92.463759)
(xy 142.659354 92.472591)
(xy 142.657174 92.475166)
(xy 142.400145 92.70216)
(xy 142.391675 92.705068)
(xy 142.384655 92.70216)
(xy 142.127625 92.475166)
(xy 142.123692 92.467121)
(xy 142.12397 92.463763)
(xy 142.190303 92.177062)
(xy 142.195507 92.169775)
(xy 142.201702 92.168)
(xy 142.583098 92.168)
)
)
)
(zone (net 13) (net_name "VDD") (layer "F.Cu") (tstamp 237c1f9b-b1c6-47e0-abda-3e7163b7beb2) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30026)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 143.9906 95.026223)
(xy 143.7406 95.026223)
(xy 143.9492 95.593895)
(xy 144.2192 95.505)
(xy 144.31778 95.184)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 143.993007 95.027383)
(xy 144.308727 95.179634)
(xy 144.31469 95.186315)
(xy 144.314829 95.193608)
(xy 144.220976 95.499214)
(xy 144.215272 95.506116)
(xy 144.213451 95.506892)
(xy 143.95994 95.590358)
(xy 143.95101 95.58969)
(xy 143.9453 95.583282)
(xy 143.746382 95.041957)
(xy 143.746745 95.033011)
(xy 143.753328 95.026941)
(xy 143.757364 95.026223)
(xy 143.987926 95.026223)
)
)
)
(zone (net 13) (net_name "VDD") (layer "F.Cu") (tstamp 25b4f947-2f8f-401e-a8a5-a107e40daadd) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30017)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 143.946351 95.407928)
(xy 144.123128 95.231151)
(xy 144.235152 94.742673)
(xy 143.864893 94.588893)
(xy 143.582757 94.872443)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 143.872136 94.591901)
(xy 144.226027 94.738883)
(xy 144.232353 94.745221)
(xy 144.232943 94.752303)
(xy 144.123879 95.227872)
(xy 144.120748 95.23353)
(xy 143.956355 95.397923)
(xy 143.948082 95.40135)
(xy 143.939809 95.397923)
(xy 143.938405 95.396226)
(xy 143.588176 94.880425)
(xy 143.586365 94.871657)
(xy 143.589561 94.865603)
(xy 143.859359 94.594453)
(xy 143.867622 94.591007)
)
)
)
(zone (net 13) (net_name "VDD") (layer "F.Cu") (tstamp 287f4d93-7e7f-4c65-ad80-75501e75f719) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30025)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 154.5024 94.59)
(xy 154.5024 94.89)
(xy 154.855738 94.999724)
(xy 155.0934 94.74)
(xy 154.855738 94.480276)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 154.857565 94.483297)
(xy 154.86075 94.485753)
(xy 155.086172 94.732102)
(xy 155.089229 94.740518)
(xy 155.086172 94.747898)
(xy 154.86075 94.994246)
(xy 154.852636 94.998037)
(xy 154.848648 94.997522)
(xy 154.51063 94.892555)
(xy 154.503746 94.886828)
(xy 154.5024 94.881381)
(xy 154.5024 94.598618)
(xy 154.505827 94.590345)
(xy 154.510629 94.587444)
(xy 154.848649 94.482477)
)
)
)
(zone (net 15) (net_name "SPI_CS") (layer "F.Cu") (tstamp 2e12fc84-a2fc-486c-98a9-20a88de95040) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30005)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 154.504795 98.351182)
(xy 154.328018 98.174405)
(xy 153.9575 97.948172)
(xy 153.456793 98.806707)
(xy 153.9575 99.097635)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 153.967486 97.954272)
(xy 153.967671 97.954382)
(xy 154.326829 98.173679)
(xy 154.329005 98.175392)
(xy 154.497697 98.344084)
(xy 154.501124 98.352357)
(xy 154.49886 98.359275)
(xy 153.963719 99.089152)
(xy 153.956063 99.093798)
(xy 153.948405 99.09235)
(xy 153.466925 98.812594)
(xy 153.461493 98.805475)
(xy 153.462686 98.796601)
(xy 153.951485 97.958484)
(xy 153.958613 97.953064)
)
)
)
(zone (net 15) (net_name "SPI_CS") (layer "F.Cu") (tstamp 30fdda52-11dd-406e-b196-ae874c3fcbbf) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30012)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 147.435 95.055775)
(xy 147.185 95.055775)
(xy 147.087508 95.809)
(xy 147.487508 95.81)
(xy 147.770351 95.526157)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 147.437245 95.059202)
(xy 147.438499 95.060683)
(xy 147.479405 95.11806)
(xy 147.481534 95.125871)
(xy 147.480736 95.134994)
(xy 147.491781 95.176216)
(xy 147.492002 95.177212)
(xy 147.499412 95.219231)
(xy 147.499413 95.219235)
(xy 147.505911 95.230489)
(xy 147.50708 95.23331)
(xy 147.510446 95.245871)
(xy 147.510447 95.245872)
(xy 147.534921 95.280826)
(xy 147.53547 95.281687)
(xy 147.556805 95.318641)
(xy 147.589503 95.346078)
(xy 147.590255 95.346768)
(xy 147.761738 95.518252)
(xy 147.765165 95.526525)
(xy 147.761753 95.534784)
(xy 147.490949 95.806546)
(xy 147.482682 95.809987)
(xy 147.482632 95.809987)
(xy 147.100786 95.809033)
(xy 147.092521 95.805585)
(xy 147.089115 95.797304)
(xy 147.089211 95.795838)
(xy 147.18368 95.065972)
(xy 147.18814 95.058208)
(xy 147.195283 95.055775)
(xy 147.428972 95.055775)
)
)
)
(zone (net 15) (net_name "SPI_CS") (layer "F.Cu") (tstamp 34dac718-1d6d-4b42-bb6e-36822c920151) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30014)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 152.030796 96.1878)
(xy 152.030796 95.9378)
(xy 151.61139 95.526157)
(xy 151.327547 95.809)
(xy 151.328547 96.209)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 151.619647 95.534261)
(xy 152.027292 95.934361)
(xy 152.030795 95.942601)
(xy 152.030796 95.94271)
(xy 152.030796 96.176447)
(xy 152.027369 96.18472)
(xy 152.019449 96.188142)
(xy 151.340569 96.208637)
(xy 151.332196 96.205461)
(xy 151.328521 96.197295)
(xy 151.328517 96.197042)
(xy 151.327559 95.813874)
(xy 151.330965 95.805594)
(xy 151.603194 95.534323)
(xy 151.611473 95.530912)
)
)
)
(zone (net 4) (net_name "SPI_MOSI") (layer "F.Cu") (tstamp 358eaad3-4699-4325-ac5e-7ded7472a25b) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30000)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 147.3325 100.681)
(xy 147.5825 100.681)
(xy 147.9575 100.181)
(xy 147.4575 98.805)
(xy 146.9575 100.181)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 147.468101 98.834309)
(xy 147.468497 98.835263)
(xy 147.955337 100.175049)
(xy 147.954941 100.183995)
(xy 147.9537 100.186065)
(xy 147.58601 100.67632)
(xy 147.578305 100.680882)
(xy 147.57665 100.681)
(xy 147.33835 100.681)
(xy 147.330077 100.677573)
(xy 147.32899 100.67632)
(xy 146.961299 100.186065)
(xy 146.959077 100.17739)
(xy 146.959662 100.175049)
(xy 147.446503 98.835263)
(xy 147.45255 98.828658)
(xy 147.461496 98.828262)
)
)
)
(zone (net 15) (net_name "SPI_CS") (layer "F.Cu") (tstamp 434edd18-7c15-465c-adf8-1045f5ba4108) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30032)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 154.9674 96.3)
(xy 155.2174 96.3)
(xy 155.3624 95.997447)
(xy 155.0924 95.759)
(xy 154.8224 95.997447)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 155.100143 95.765838)
(xy 155.355772 95.991593)
(xy 155.359705 95.999638)
(xy 155.358578 96.00542)
(xy 155.220584 96.293357)
(xy 155.213918 96.299336)
(xy 155.210033 96.3)
(xy 154.974767 96.3)
(xy 154.966494 96.296573)
(xy 154.964216 96.293357)
(xy 154.826221 96.00542)
(xy 154.825736 95.996478)
(xy 154.829024 95.991596)
(xy 155.084656 95.765838)
(xy 155.093125 95.762931)
)
)
)
(zone (net 13) (net_name "VDD") (layer "F.Cu") (tstamp 44b1268f-c241-4cca-bb2a-4b6e028e8849) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30030)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 150.55309 95.226242)
(xy 150.340958 95.01411)
(xy 150.0808 94.97)
(xy 149.910093 95.250707)
(xy 150.192318 95.470251)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 150.337279 95.013486)
(xy 150.343596 95.016748)
(xy 150.543067 95.216219)
(xy 150.546494 95.224492)
(xy 150.543067 95.232765)
(xy 150.541349 95.234183)
(xy 150.199353 95.465492)
(xy 150.19058 95.467289)
(xy 150.185614 95.465036)
(xy 149.918324 95.25711)
(xy 149.913898 95.249325)
(xy 149.91551 95.241798)
(xy 150.076675 94.976781)
(xy 150.083901 94.971495)
(xy 150.088627 94.971327)
)
)
)
(zone (net 13) (net_name "VDD") (layer "F.Cu") (tstamp 596f313c-8432-4f58-8698-d4ad55d2cbe7) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30022)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 145.66 87.8852)
(xy 145.96 87.8852)
(xy 146.081461 87.539551)
(xy 145.796 87.3242)
(xy 145.521703 87.556261)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 145.803464 87.329831)
(xy 146.074633 87.5344)
(xy 146.079174 87.542118)
(xy 146.078625 87.547619)
(xy 145.962748 87.877379)
(xy 145.956773 87.884048)
(xy 145.95171 87.8852)
(xy 145.667774 87.8852)
(xy 145.659501 87.881773)
(xy 145.656988 87.878035)
(xy 145.525032 87.564179)
(xy 145.524985 87.555224)
(xy 145.528259 87.550714)
(xy 145.788862 87.330238)
(xy 145.797391 87.327511)
)
)
)
(zone (net 5) (net_name "SPI_MISO") (layer "F.Cu") (tstamp 59fba88c-f42d-4ada-8fa0-f1bc2e846989) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30013)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 145.3325 97.110326)
(xy 145.5825 97.110326)
(xy 145.287052 96.380927)
(xy 144.9175 96.533)
(xy 144.764427 96.903552)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 145.285126 96.385424)
(xy 145.291444 96.391771)
(xy 145.291468 96.39183)
(xy 145.575981 97.094233)
(xy 145.575911 97.103188)
(xy 145.56953 97.10947)
(xy 145.565137 97.110326)
(xy 145.334562 97.110326)
(xy 145.33056 97.10962)
(xy 145.312889 97.103188)
(xy 144.7759 96.907728)
(xy 144.769298 96.901678)
(xy 144.768908 96.892732)
(xy 144.769076 96.892296)
(xy 144.915641 96.537498)
(xy 144.921965 96.531162)
(xy 145.276174 96.385403)
)
)
)
(zone (net 3) (net_name "SPI_CLK") (layer "F.Cu") (tstamp 6b5e369b-803a-4cd9-a9e2-0d094985c2d8) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30015)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 146.935 94.948161)
(xy 146.685 94.948161)
(xy 146.219853 95.197568)
(xy 146.372926 95.56812)
(xy 146.742478 95.720193)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 146.928297 94.951588)
(xy 146.931724 94.959861)
(xy 146.931376 94.962692)
(xy 146.745755 95.707049)
(xy 146.740429 95.714247)
(xy 146.731572 95.71557)
(xy 146.729951 95.715038)
(xy 146.377429 95.569973)
(xy 146.371082 95.563655)
(xy 146.371067 95.56362)
(xy 146.223892 95.207346)
(xy 146.223901 95.198391)
(xy 146.229175 95.192569)
(xy 146.682409 94.949549)
(xy 146.687938 94.948161)
(xy 146.920024 94.948161)
)
)
)
(zone (net 13) (net_name "VDD") (layer "F.Cu") (tstamp 6db6869c-e92a-48e5-8583-e1399aae49bf) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30007)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 153.9742 92.1386)
(xy 153.5742 92.1386)
(xy 153.404648 92.785527)
(xy 153.7742 92.9396)
(xy 154.143752 92.785527)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 153.973444 92.142027)
(xy 153.976489 92.147334)
(xy 154.141171 92.775679)
(xy 154.139953 92.78455)
(xy 154.134355 92.789444)
(xy 153.778702 92.937723)
(xy 153.769748 92.937744)
(xy 153.769698 92.937723)
(xy 153.414044 92.789444)
(xy 153.407726 92.783097)
(xy 153.407228 92.775682)
(xy 153.571911 92.147334)
(xy 153.577324 92.1402)
(xy 153.583229 92.1386)
(xy 153.965171 92.1386)
)
)
)
(zone (net 13) (net_name "VDD") (layer "F.Cu") (tstamp 8075af7b-b9e1-4a97-96e6-8f1b49a1479f) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30009)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 140.9668 90.9448)
(xy 140.5668 90.9448)
(xy 140.397248 91.591727)
(xy 140.7668 91.7458)
(xy 141.136352 91.591727)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 140.966044 90.948227)
(xy 140.969089 90.953534)
(xy 141.133771 91.581879)
(xy 141.132553 91.59075)
(xy 141.126955 91.595644)
(xy 140.771302 91.743923)
(xy 140.762348 91.743944)
(xy 140.762298 91.743923)
(xy 140.406644 91.595644)
(xy 140.400326 91.589297)
(xy 140.399828 91.581882)
(xy 140.564511 90.953534)
(xy 140.569924 90.9464)
(xy 140.575829 90.9448)
(xy 140.957771 90.9448)
)
)
)
(zone (net 14) (net_name "RESET") (layer "F.Cu") (tstamp 95de982e-53d8-4f2f-84d7-a1bcc0b92930) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30003)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 142.692335 97.420059)
(xy 142.515559 97.596835)
(xy 142.9575 98.955378)
(xy 143.458207 98.806707)
(xy 143.15152 97.431)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 142.697318 97.420177)
(xy 143.142372 97.430782)
(xy 143.150559 97.434404)
(xy 143.153511 97.439932)
(xy 143.455831 98.796052)
(xy 143.454286 98.804873)
(xy 143.447741 98.809814)
(xy 142.968429 98.952132)
(xy 142.959523 98.951202)
(xy 142.953973 98.944535)
(xy 142.810931 98.504822)
(xy 142.517777 97.603653)
(xy 142.518476 97.594728)
(xy 142.520627 97.591766)
(xy 142.688792 97.423601)
(xy 142.697064 97.420175)
)
)
)
(zone (net 5) (net_name "SPI_MISO") (layer "F.Cu") (tstamp b71c94c3-876b-4a72-8df2-4f831d6bc223) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30016)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 151.307216 93.067207)
(xy 151.483993 93.243984)
(xy 152.0952 93.3132)
(xy 152.095907 92.912493)
(xy 151.812357 92.630357)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 151.820051 92.638013)
(xy 152.09245 92.909053)
(xy 152.095898 92.917318)
(xy 152.095898 92.917368)
(xy 152.095223 93.300123)
(xy 152.091782 93.30839)
(xy 152.083502 93.311802)
(xy 152.082206 93.311728)
(xy 151.488056 93.244444)
(xy 151.4811 93.241091)
(xy 151.31611 93.076101)
(xy 151.312683 93.067828)
(xy 151.31611 93.059555)
(xy 151.316711 93.058995)
(xy 151.804147 92.637456)
(xy 151.812645 92.634638)
)
)
)
(zone (net 3) (net_name "SPI_CLK") (layer "F.Cu") (tstamp b74a087e-b0de-4327-bdce-b1743022fba3) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30006)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 140.58083 98.189254)
(xy 140.404054 98.36603)
(xy 140.9575 99.10252)
(xy 141.458207 98.806707)
(xy 140.9575 97.962299)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 140.963466 97.972362)
(xy 140.963509 97.972433)
(xy 141.45223 98.796627)
(xy 141.453502 98.80549)
(xy 141.448133 98.812658)
(xy 141.448117 98.812667)
(xy 140.966514 99.097194)
(xy 140.957648 99.098452)
(xy 140.95121 99.09415)
(xy 140.410154 98.374148)
(xy 140.407924 98.365477)
(xy 140.411234 98.358849)
(xy 140.579824 98.190259)
(xy 140.582049 98.188518)
(xy 140.947409 97.968378)
(xy 140.956262 97.967044)
)
)
)
(zone (net 14) (net_name "RESET") (layer "F.Cu") (tstamp bb560d0e-aa61-4482-8efe-3fdff0767503) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30031)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 142.2674 94.268)
(xy 142.5174 94.268)
(xy 142.6624 93.965447)
(xy 142.3924 93.727)
(xy 142.1224 93.965447)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 142.400143 93.733838)
(xy 142.655772 93.959593)
(xy 142.659705 93.967638)
(xy 142.658578 93.97342)
(xy 142.520584 94.261357)
(xy 142.513918 94.267336)
(xy 142.510033 94.268)
(xy 142.274767 94.268)
(xy 142.266494 94.264573)
(xy 142.264216 94.261357)
(xy 142.126221 93.97342)
(xy 142.125736 93.964478)
(xy 142.129024 93.959596)
(xy 142.384656 93.733838)
(xy 142.393125 93.730931)
)
)
)
(zone (net 2) (net_name "IRQ") (layer "F.Cu") (tstamp c2b32c07-f1a9-46a2-8278-cbadeeaa2113) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30001)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 145.5825 103.181)
(xy 145.3325 103.181)
(xy 144.9575 103.681)
(xy 145.4575 105.057)
(xy 145.9575 103.681)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 145.584923 103.184427)
(xy 145.58601 103.18568)
(xy 145.9537 103.675934)
(xy 145.955922 103.684609)
(xy 145.955337 103.68695)
(xy 145.468497 105.026736)
(xy 145.46245 105.033341)
(xy 145.453504 105.033737)
(xy 145.446899 105.02769)
(xy 145.446503 105.026736)
(xy 144.959662 103.68695)
(xy 144.960058 103.678004)
(xy 144.961297 103.675937)
(xy 145.32899 103.18568)
(xy 145.336695 103.181118)
(xy 145.33835 103.181)
(xy 145.57665 103.181)
)
)
)
(zone (net 15) (net_name "SPI_CS") (layer "F.Cu") (tstamp c64c4473-8d3c-43c2-bb4b-7617762fdff9) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30028)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 154.5024 95.635)
(xy 154.5024 95.885)
(xy 154.855738 96.019724)
(xy 155.0934 95.76)
(xy 154.855738 95.500276)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 154.857257 95.503363)
(xy 154.861106 95.506143)
(xy 155.086172 95.752102)
(xy 155.089229 95.760518)
(xy 155.086172 95.767898)
(xy 154.861106 96.013856)
(xy 154.852992 96.017647)
(xy 154.848306 96.01689)
(xy 154.509932 95.887871)
(xy 154.503422 95.881722)
(xy 154.5024 95.876939)
(xy 154.5024 95.64306)
(xy 154.505827 95.634787)
(xy 154.509932 95.632128)
(xy 154.848307 95.503109)
)
)
)
(zone (net 2) (net_name "IRQ") (layer "F.Cu") (tstamp c715f889-40cf-4bc2-8221-87d050c9bd3c) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30033)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 145.522926 95.635274)
(xy 145.772926 95.635274)
(xy 145.506562 95.305737)
(xy 145.2392 95.503)
(xy 145.425862 95.813724)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 145.513599 95.314443)
(xy 145.757524 95.616219)
(xy 145.76006 95.624807)
(xy 145.75578 95.632673)
(xy 145.748425 95.635274)
(xy 145.522924 95.635274)
(xy 145.435635 95.795755)
(xy 145.428672 95.801386)
(xy 145.419767 95.800443)
(xy 145.415329 95.796191)
(xy 145.244678 95.51212)
(xy 145.243356 95.503265)
(xy 145.24776 95.496683)
(xy 145.497554 95.312382)
(xy 145.506245 95.310229)
)
)
)
(zone (net 14) (net_name "RESET") (layer "F.Cu") (tstamp ca2b5349-9bd0-407a-8439-241a745039e2) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30027)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 142.9824 93.8755)
(xy 142.9824 93.6255)
(xy 142.629062 93.468276)
(xy 142.3914 93.728)
(xy 142.629062 93.987724)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 142.636758 93.4717)
(xy 142.975456 93.62241)
(xy 142.981622 93.628905)
(xy 142.9824 93.6331)
(xy 142.9824 93.86694)
(xy 142.978973 93.875213)
(xy 142.974242 93.878091)
(xy 142.636188 93.98546)
(xy 142.627265 93.984698)
(xy 142.624014 93.982207)
(xy 142.398627 93.735898)
(xy 142.39557 93.727482)
(xy 142.398627 93.720102)
(xy 142.623373 93.474492)
(xy 142.631486 93.470702)
)
)
)
(zone (net 13) (net_name "VDD") (layer "F.Cu") (tstamp cfe32eff-a6d2-4014-b799-a87b35e0d115) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30029)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 149.409615 95.16058)
(xy 149.23284 95.337355)
(xy 149.687224 95.519343)
(xy 149.911507 95.250707)
(xy 149.687224 94.980657)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 149.693865 94.988653)
(xy 149.905282 95.243212)
(xy 149.907931 95.251766)
(xy 149.905262 95.258185)
(xy 149.692668 95.512821)
(xy 149.684736 95.516976)
(xy 149.679337 95.516184)
(xy 149.249303 95.343948)
(xy 149.242897 95.337691)
(xy 149.242792 95.328737)
(xy 149.245378 95.324816)
(xy 149.408747 95.161447)
(xy 149.410646 95.159911)
(xy 149.678502 94.986309)
(xy 149.687307 94.984686)
)
)
)
(zone (net 13) (net_name "VDD") (layer "F.Cu") (tstamp dcb9bbce-45f2-4be6-9c44-d3b3e4dcbcc7) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30019)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 146.386 87.5252)
(xy 146.386 87.1252)
(xy 145.966 87.0452)
(xy 145.795 87.3252)
(xy 145.966 87.6052)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 146.083735 87.067625)
(xy 146.376489 87.123388)
(xy 146.383975 87.128302)
(xy 146.386 87.134881)
(xy 146.386 87.515518)
(xy 146.382573 87.523791)
(xy 146.376489 87.527011)
(xy 145.973953 87.603684)
(xy 145.965185 87.601866)
(xy 145.961779 87.598289)
(xy 145.798724 87.331298)
(xy 145.797336 87.322451)
(xy 145.798724 87.319102)
(xy 145.96178 87.052108)
(xy 145.969015 87.046835)
(xy 145.973953 87.046715)
)
)
)
(zone (net 3) (net_name "SPI_CLK") (layer "F.Cu") (tstamp f9f098d4-f3b8-43b0-9a06-db6e4d6e4a47) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30011)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 139.7125 96.826)
(xy 139.9625 96.826)
(xy 140.207052 96.179073)
(xy 139.8375 96.025)
(xy 139.467948 96.179073)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 140.196609 96.174719)
(xy 140.202927 96.181066)
(xy 140.203051 96.189655)
(xy 139.965359 96.818437)
(xy 139.959228 96.824964)
(xy 139.954415 96.826)
(xy 139.720585 96.826)
(xy 139.712312 96.822573)
(xy 139.709641 96.818437)
(xy 139.471948 96.189655)
(xy 139.472228 96.180705)
(xy 139.478389 96.174719)
(xy 139.833 96.026875)
(xy 139.841949 96.026855)
)
)
)
(zone (net 13) (net_name "VDD") (layer "F.Cu") (tstamp fbaed023-f13e-4849-a65b-7b83638ddcaf) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30021)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 153.5742 91.6236)
(xy 153.9742 91.6236)
(xy 154.0288 91.2036)
(xy 153.7488 91.0326)
(xy 153.479457 91.257176)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 153.755951 91.036967)
(xy 154.022316 91.19964)
(xy 154.027591 91.206876)
(xy 154.02782 91.211133)
(xy 153.975525 91.613408)
(xy 153.971061 91.621171)
(xy 153.963923 91.6236)
(xy 153.583259 91.6236)
(xy 153.574986 91.620173)
(xy 153.571932 91.614829)
(xy 153.481311 91.264348)
(xy 153.482557 91.25548)
(xy 153.485145 91.252433)
(xy 153.534678 91.211133)
(xy 153.742363 91.037966)
(xy 153.750911 91.035301)
)
)
)
New branch for new revision
2024-03-12 11:46:53 +01:00
(zone (net 1) (net_name "GND") (layers "F&B.Cu") (tstamp 9aa33cab-3101-42a6-83d2-bdb43d93501b) (name "Groundplane") (hatch edge 0.5)
(connect_pads (clearance 0.25))
(min_thickness 0.25) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (smoothing chamfer))
(polygon
(pts
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 137.681323 83.904365)
(xy 157.1752 83.9216)
(xy 157.1752 108.331)
(xy 137.681323 108.313765)
New branch for new revision
2024-03-12 11:46:53 +01:00
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 153.875384 94.806585)
(xy 153.896026 94.823219)
(xy 154.122613 95.049807)
(xy 154.122633 95.049825)
(xy 154.140856 95.068049)
(xy 154.160594 95.078106)
(xy 154.177182 95.088271)
(xy 154.19511 95.101296)
(xy 154.216179 95.108141)
(xy 154.234158 95.115588)
(xy 154.253896 95.125646)
(xy 154.275778 95.129111)
(xy 154.294691 95.133652)
(xy 154.315767 95.1405)
(xy 154.315772 95.1405)
(xy 154.325404 95.142026)
(xy 154.325121 95.143812)
(xy 154.380879 95.160185)
(xy 154.426634 95.212989)
(xy 154.436578 95.282147)
(xy 154.407553 95.345703)
(xy 154.348775 95.383477)
(xy 154.334246 95.386809)
(xy 154.327599 95.387918)
(xy 154.322538 95.388656)
(xy 154.312899 95.389857)
(xy 154.27057 95.395134)
(xy 154.263057 95.397371)
(xy 154.255586 95.399936)
(xy 154.209571 95.424837)
(xy 154.20502 95.42718)
(xy 154.157992 95.450171)
(xy 154.151575 95.454753)
(xy 154.145375 95.459579)
(xy 154.109931 95.498081)
(xy 154.106385 95.501777)
(xy 153.957179 95.650982)
(xy 153.895859 95.684466)
(xy 153.8695 95.6873)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 152.19101 95.6873)
(xy 152.123971 95.667615)
(xy 152.104152 95.651796)
(xy 152.087697 95.635646)
(xy 151.798618 95.351917)
(xy 151.798619 95.351917)
(xy 151.795017 95.349545)
(xy 151.786331 95.343823)
(xy 151.772323 95.333091)
(xy 151.753576 95.316483)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 151.700787 95.269717)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 151.700779 95.269713)
(xy 151.700778 95.269712)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 151.68591 95.261908)
(xy 151.635699 95.213323)
(xy 151.619725 95.145304)
(xy 151.643061 95.079446)
(xy 151.67064 95.051805)
(xy 151.687633 95.039458)
(xy 151.704188 95.029314)
(xy 151.723942 95.01925)
(xy 151.739434 95.003757)
(xy 151.739441 95.003752)
(xy 151.812527 94.930666)
(xy 151.919973 94.823218)
(xy 151.981296 94.789734)
(xy 152.007654 94.7869)
(xy 153.808345 94.7869)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 145.390692 94.145685)
(xy 145.436447 94.198489)
(xy 145.437505 94.201336)
(xy 145.477855 94.287866)
(xy 145.48715 94.307799)
(xy 145.565201 94.38585)
(xy 145.66524 94.432499)
(xy 145.668632 94.432945)
(xy 145.672229 94.434536)
(xy 145.674351 94.435155)
(xy 145.674268 94.435438)
(xy 145.73253 94.461207)
(xy 145.771005 94.519528)
(xy 145.771842 94.589393)
(xy 145.740136 94.643566)
(xy 145.486522 94.897181)
(xy 145.425199 94.930666)
(xy 145.398841 94.9335)
(xy 145.067618 94.9335)
(xy 144.992682 94.944418)
(xy 144.99268 94.944418)
(xy 144.992678 94.944419)
(xy 144.8771 95.000921)
(xy 144.877097 95.000923)
(xy 144.816881 95.06114)
(xy 144.755558 95.094625)
(xy 144.685866 95.089641)
(xy 144.641519 95.06114)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 144.581303 95.000924)
(xy 144.540893 94.981168)
(xy 144.489311 94.934039)
(xy 144.471398 94.866505)
(xy 144.474491 94.842057)
(xy 144.481978 94.809415)
(xy 144.481979 94.8094)
(xy 144.482628 94.80506)
(xy 144.489324 94.779409)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 144.501837 94.746418)
(xy 144.520878 94.5896)
(xy 144.501837 94.432782)
(xy 144.449192 94.29397)
(xy 144.443826 94.224308)
(xy 144.476973 94.162802)
(xy 144.538112 94.12898)
(xy 144.565135 94.126)
(xy 145.323653 94.126)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 152.635473 87.795385)
(xy 152.656115 87.812019)
(xy 153.261981 88.417884)
(xy 153.295466 88.479207)
(xy 153.2983 88.505565)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 153.2983 90.381522)
(xy 153.29611 90.404724)
(xy 153.253471 90.628577)
(xy 153.219328 90.807838)
(xy 153.219327 90.807841)
(xy 153.219326 90.807843)
(xy 153.21489 90.861859)
(xy 153.215009 90.866787)
(xy 153.215009 90.866788)
(xy 153.217242 90.883764)
(xy 153.2183 90.89993)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 153.2183 91.234339)
(xy 153.232782 91.325774)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 153.234103 91.32984)
(xy 153.236223 91.337114)
(xy 153.319477 91.659103)
(xy 153.319752 91.660164)
(xy 153.3237 91.691205)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 153.3237 91.959468)
(xy 153.320591 91.98706)
(xy 153.319884 91.990154)
(xy 153.323353 92.036428)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 153.3237 92.045696)
(xy 153.3237 92.070617)
(xy 153.319649 92.102054)
(xy 153.160076 92.710906)
(xy 153.160074 92.710917)
(xy 153.160062 92.711045)
(xy 153.160017 92.711235)
(xy 153.1592 92.715846)
(xy 153.158955 92.715802)
(xy 153.152561 92.743287)
(xy 153.137962 92.781782)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 153.118922 92.938599)
(xy 153.118922 92.9386)
(xy 153.137962 93.095418)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 153.188488 93.228643)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 153.19398 93.243123)
(xy 153.283717 93.37313)
(xy 153.40196 93.477883)
(xy 153.401962 93.477884)
(xy 153.541834 93.551296)
(xy 153.695214 93.5891)
(xy 153.695215 93.5891)
(xy 153.853185 93.5891)
(xy 154.006565 93.551296)
(xy 154.05496 93.525896)
(xy 154.14644 93.477883)
(xy 154.264683 93.37313)
(xy 154.35442 93.243123)
(xy 154.401958 93.117774)
(xy 154.444136 93.062072)
(xy 154.509733 93.038015)
(xy 154.577924 93.053242)
(xy 154.627057 93.102918)
(xy 154.6419 93.161746)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 154.6419 94.13506)
(xy 154.638691 94.163087)
(xy 154.638336 94.164617)
(xy 154.604009 94.225472)
(xy 154.542229 94.258108)
(xy 154.472613 94.252163)
(xy 154.429865 94.224272)
(xy 154.286509 94.080916)
(xy 154.286508 94.080915)
(xy 154.283397 94.077804)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 154.283382 94.07779)
(xy 154.263942 94.05835)
(xy 154.26394 94.058349)
(xy 154.2442 94.04829)
(xy 154.227614 94.038126)
(xy 154.20969 94.025104)
(xy 154.209691 94.025104)
(xy 154.188618 94.018257)
(xy 154.170645 94.010812)
(xy 154.150907 94.000755)
(xy 154.150904 94.000754)
(xy 154.129018 93.997287)
(xy 154.110107 93.992746)
(xy 154.089039 93.985901)
(xy 154.089034 93.9859)
(xy 154.089033 93.9859)
(xy 154.057119 93.9859)
(xy 151.758881 93.9859)
(xy 151.75377 93.9859)
(xy 151.753746 93.985901)
(xy 151.726964 93.985901)
(xy 151.705899 93.992746)
(xy 151.686982 93.997287)
(xy 151.6651 94.000752)
(xy 151.665095 94.000754)
(xy 151.64535 94.010814)
(xy 151.627386 94.018255)
(xy 151.606307 94.025105)
(xy 151.588384 94.038127)
(xy 151.571799 94.04829)
(xy 151.552059 94.058348)
(xy 151.54591 94.064498)
(xy 151.529492 94.080916)
(xy 151.529491 94.080917)
(xy 151.356026 94.254381)
(xy 151.294703 94.287866)
(xy 151.268345 94.2907)
(xy 151.086322 94.2907)
(xy 151.019283 94.271015)
(xy 150.973528 94.218211)
(xy 150.963584 94.149053)
(xy 150.992609 94.085497)
(xy 151.014267 94.065784)
(xy 151.028294 94.055768)
(xy 151.03452 94.050922)
(xy 151.034526 94.050919)
(xy 151.070016 94.012365)
(xy 151.073494 94.008741)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 151.528986 93.553249)
(xy 151.590307 93.519766)
(xy 151.630616 93.51772)
(xy 151.927103 93.551296)
(xy 151.990902 93.558521)
(xy 152.006622 93.561335)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 152.016215 93.5637)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 152.029639 93.5637)
(xy 152.043592 93.564488)
(xy 152.053456 93.565605)
(xy 152.067641 93.566813)
(xy 152.068937 93.566887)
(xy 152.080216 93.567219)
(xy 152.083032 93.567302)
(xy 152.083035 93.567302)
(xy 152.083035 93.567301)
(xy 152.083036 93.567302)
(xy 152.089446 93.566038)
(xy 152.113418 93.5637)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 152.174185 93.5637)
(xy 152.327565 93.525896)
(xy 152.46744 93.452483)
(xy 152.585683 93.34773)
(xy 152.67542 93.217723)
(xy 152.731437 93.070018)
(xy 152.750478 92.9132)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 152.746312 92.878885)
(xy 152.731437 92.756381)
(xy 152.695711 92.66218)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 152.67542 92.608677)
(xy 152.585683 92.47867)
(xy 152.46744 92.373917)
(xy 152.467438 92.373916)
(xy 152.467437 92.373915)
(xy 152.327565 92.300503)
(xy 152.174186 92.2627)
(xy 152.174185 92.2627)
(xy 152.016215 92.2627)
(xy 152.016214 92.2627)
(xy 151.862834 92.300503)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 151.722964 92.373914)
(xy 151.722956 92.373919)
(xy 151.665139 92.425139)
(xy 151.644178 92.440131)
(xy 151.637015 92.4442)
(xy 151.637011 92.444204)
(xy 151.515686 92.549126)
(xy 151.49359 92.56439)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 151.468371 92.578037)
(xy 151.46382 92.58038)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 151.41679 92.603372)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 151.410375 92.607953)
(xy 151.404174 92.612779)
(xy 151.368718 92.651294)
(xy 151.365172 92.654989)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 151.188581 92.83158)
(xy 151.182015 92.837687)
(xy 151.149617 92.865707)
(xy 151.142503 92.872094)
(xy 151.141947 92.872611)
(xy 151.135453 92.878879)
(xy 151.135444 92.878889)
(xy 151.130487 92.886308)
(xy 151.115072 92.905089)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 150.89718 93.122981)
(xy 150.835857 93.156466)
(xy 150.766165 93.151482)
(xy 150.710232 93.10961)
(xy 150.685815 93.044146)
(xy 150.685499 93.0353)
(xy 150.685499 92.963819)
(xy 150.679499 92.918243)
(xy 150.679499 92.918242)
(xy 150.679499 92.91824)
(xy 150.65486 92.865403)
(xy 150.644369 92.796327)
(xy 150.654858 92.760601)
(xy 150.679499 92.70776)
(xy 150.6855 92.662179)
(xy 150.685499 92.463822)
(xy 150.679499 92.41824)
(xy 150.65486 92.365403)
(xy 150.644369 92.296327)
(xy 150.654858 92.260601)
(xy 150.679499 92.20776)
(xy 150.6855 92.162179)
(xy 150.685499 91.963822)
(xy 150.679499 91.91824)
(xy 150.65486 91.865403)
(xy 150.644369 91.796327)
(xy 150.654858 91.760601)
(xy 150.679499 91.70776)
(xy 150.6855 91.662179)
(xy 150.685499 91.463822)
(xy 150.679499 91.41824)
(xy 150.65486 91.365403)
(xy 150.644369 91.296327)
(xy 150.654858 91.260601)
(xy 150.679499 91.20776)
(xy 150.6855 91.162179)
(xy 150.685499 90.963822)
(xy 150.679499 90.91824)
(xy 150.65486 90.865403)
(xy 150.644369 90.796327)
(xy 150.654858 90.760601)
(xy 150.679499 90.70776)
(xy 150.6855 90.662179)
(xy 150.685499 90.463822)
(xy 150.679499 90.41824)
(xy 150.65486 90.365403)
(xy 150.644369 90.296327)
(xy 150.654858 90.260601)
(xy 150.679499 90.20776)
(xy 150.6855 90.162179)
(xy 150.685499 89.963822)
(xy 150.679499 89.91824)
(xy 150.63285 89.818201)
(xy 150.554799 89.74015)
(xy 150.45476 89.693501)
(xy 150.454758 89.6935)
(xy 150.409188 89.687501)
(xy 150.409185 89.6875)
(xy 150.409179 89.6875)
(xy 150.409172 89.6875)
(xy 149.67751 89.6875)
(xy 149.610471 89.667815)
(xy 149.564716 89.615011)
(xy 149.554772 89.545853)
(xy 149.583797 89.482297)
(xy 149.589816 89.475832)
(xy 149.63285 89.432799)
(xy 149.679499 89.33276)
(xy 149.6855 89.287179)
(xy 149.6855 88.906614)
(xy 149.6855 87.8997)
(xy 149.705185 87.832661)
(xy 149.757989 87.786906)
(xy 149.8095 87.7757)
(xy 152.568434 87.7757)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 148.877539 87.795385)
(xy 148.923294 87.848189)
(xy 148.9345 87.8997)
(xy 148.9345 89.28718)
(xy 148.9405 89.332756)
(xy 148.940502 89.332763)
(xy 148.956051 89.366108)
(xy 148.98715 89.432799)
(xy 149.065201 89.51085)
(xy 149.16524 89.557499)
(xy 149.210821 89.5635)
(xy 149.317489 89.563499)
(xy 149.384528 89.583183)
(xy 149.430283 89.635987)
(xy 149.440227 89.705145)
(xy 149.411203 89.768701)
(xy 149.405171 89.775179)
(xy 149.36215 89.8182)
(xy 149.3155 89.918241)
(xy 149.309501 89.963811)
(xy 149.3095 89.963827)
(xy 149.3095 90.16218)
(xy 149.3155 90.207756)
(xy 149.315503 90.207766)
(xy 149.340138 90.260596)
(xy 149.35063 90.329673)
(xy 149.340139 90.365404)
(xy 149.3155 90.418243)
(xy 149.309501 90.463811)
(xy 149.3095 90.463827)
(xy 149.3095 90.66218)
(xy 149.3155 90.707756)
(xy 149.315503 90.707766)
(xy 149.340138 90.760596)
(xy 149.35063 90.829673)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 149.340139 90.865403)
(xy 149.331578 90.883764)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 149.3155 90.918243)
(xy 149.309501 90.963811)
(xy 149.3095 90.963827)
(xy 149.3095 91.16218)
(xy 149.3155 91.207756)
(xy 149.315503 91.207766)
(xy 149.340138 91.260596)
(xy 149.35063 91.329673)
(xy 149.340139 91.365403)
(xy 149.318957 91.41083)
(xy 149.3155 91.418243)
(xy 149.309501 91.463811)
(xy 149.3095 91.463827)
(xy 149.3095 91.66218)
(xy 149.3155 91.707756)
(xy 149.315503 91.707766)
(xy 149.340138 91.760596)
(xy 149.35063 91.829673)
(xy 149.340139 91.865404)
(xy 149.3155 91.918243)
(xy 149.309501 91.963811)
(xy 149.3095 91.963827)
(xy 149.3095 92.16218)
(xy 149.3155 92.207756)
(xy 149.315503 92.207766)
(xy 149.340138 92.260596)
(xy 149.35063 92.329673)
(xy 149.340139 92.365403)
(xy 149.321671 92.40501)
(xy 149.3155 92.418243)
(xy 149.309501 92.463811)
(xy 149.3095 92.463827)
(xy 149.3095 92.66218)
(xy 149.3155 92.707756)
(xy 149.315503 92.707766)
(xy 149.340138 92.760596)
(xy 149.35063 92.829673)
(xy 149.340139 92.865404)
(xy 149.3155 92.918242)
(xy 149.310439 92.956687)
(xy 149.282172 93.020583)
(xy 149.223848 93.059054)
(xy 149.203684 93.06344)
(xy 149.165243 93.0685)
(xy 149.165236 93.068502)
(xy 149.0652 93.11515)
(xy 148.98715 93.1932)
(xy 148.9405 93.293241)
(xy 148.934501 93.338811)
(xy 148.9345 93.338827)
(xy 148.9345 93.729828)
(xy 148.934077 93.740065)
(xy 148.933077 93.752136)
(xy 148.926109 93.770192)
(xy 148.928477 93.773876)
(xy 148.929708 93.778379)
(xy 148.930608 93.781934)
(xy 148.930608 93.781937)
(xy 148.930708 93.782334)
(xy 148.9345 93.812761)
(xy 148.9345 94.03184)
(xy 148.914815 94.098879)
(xy 148.862011 94.144634)
(xy 148.792853 94.154578)
(xy 148.729297 94.125553)
(xy 148.722819 94.119521)
(xy 148.721819 94.118521)
(xy 148.688334 94.057198)
(xy 148.6855 94.03084)
(xy 148.6855 93.808811)
(xy 148.694334 93.778724)
(xy 148.688045 93.766892)
(xy 148.6855 93.741899)
(xy 148.6855 93.711791)
(xy 148.685499 93.711773)
(xy 148.685499 93.338819)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 148.68138 93.307531)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 148.679499 93.29324)
(xy 148.63285 93.193201)
(xy 148.554799 93.11515)
(xy 148.45476 93.068501)
(xy 148.454758 93.0685)
(xy 148.409188 93.062501)
(xy 148.409185 93.0625)
(xy 148.409179 93.0625)
(xy 148.409172 93.0625)
(xy 148.210819 93.0625)
(xy 148.165243 93.0685)
(xy 148.165238 93.068501)
(xy 148.112403 93.093139)
(xy 148.043325 93.10363)
(xy 148.007595 93.093138)
(xy 147.954759 93.0685)
(xy 147.909188 93.062501)
(xy 147.909185 93.0625)
(xy 147.909179 93.0625)
(xy 147.909172 93.0625)
(xy 147.710819 93.0625)
(xy 147.665243 93.0685)
(xy 147.665238 93.068501)
(xy 147.612403 93.093139)
(xy 147.543325 93.10363)
(xy 147.507595 93.093138)
(xy 147.454759 93.0685)
(xy 147.409188 93.062501)
(xy 147.409185 93.0625)
(xy 147.409179 93.0625)
(xy 147.409172 93.0625)
(xy 147.210819 93.0625)
(xy 147.165243 93.0685)
(xy 147.165238 93.068501)
(xy 147.112403 93.093139)
(xy 147.043325 93.10363)
(xy 147.007595 93.093138)
(xy 146.954759 93.0685)
(xy 146.909188 93.062501)
(xy 146.909185 93.0625)
(xy 146.909179 93.0625)
(xy 146.909172 93.0625)
(xy 146.710819 93.0625)
(xy 146.665243 93.0685)
(xy 146.665238 93.068501)
(xy 146.612403 93.093139)
(xy 146.543325 93.10363)
(xy 146.507595 93.093138)
(xy 146.454759 93.0685)
(xy 146.409188 93.062501)
(xy 146.409185 93.0625)
(xy 146.409179 93.0625)
(xy 146.409172 93.0625)
(xy 146.210819 93.0625)
(xy 146.165243 93.0685)
(xy 146.165238 93.068501)
(xy 146.112403 93.093139)
(xy 146.043325 93.10363)
(xy 146.007595 93.093138)
(xy 145.954759 93.0685)
(xy 145.909188 93.062501)
(xy 145.909185 93.0625)
(xy 145.909179 93.0625)
(xy 145.909172 93.0625)
(xy 145.80251 93.0625)
(xy 145.735471 93.042815)
(xy 145.689716 92.990011)
(xy 145.679772 92.920853)
(xy 145.708797 92.857297)
(xy 145.714816 92.850832)
(xy 145.75785 92.807799)
(xy 145.804499 92.70776)
(xy 145.8105 92.662179)
(xy 145.810499 92.463822)
(xy 145.804499 92.41824)
(xy 145.77986 92.365403)
(xy 145.769369 92.296327)
(xy 145.779858 92.260601)
(xy 145.804499 92.20776)
(xy 145.8105 92.162179)
(xy 145.810499 91.963822)
(xy 145.804499 91.91824)
(xy 145.77986 91.865403)
(xy 145.769369 91.796327)
(xy 145.779858 91.760601)
(xy 145.804499 91.70776)
(xy 145.8105 91.662179)
(xy 145.810499 91.463822)
(xy 145.804499 91.41824)
(xy 145.77986 91.365403)
(xy 145.769369 91.296327)
(xy 145.779858 91.260601)
(xy 145.804499 91.20776)
(xy 145.8105 91.162179)
(xy 145.810499 90.963822)
(xy 145.804499 90.91824)
(xy 145.77986 90.865403)
(xy 145.769369 90.796327)
(xy 145.779858 90.760601)
(xy 145.804499 90.70776)
(xy 145.8105 90.662179)
(xy 145.810499 90.463822)
(xy 145.804499 90.41824)
(xy 145.77986 90.365403)
(xy 145.769369 90.296327)
(xy 145.779858 90.260601)
(xy 145.804499 90.20776)
(xy 145.8105 90.162179)
(xy 145.810499 89.963822)
(xy 145.804499 89.91824)
(xy 145.75785 89.818201)
(xy 145.757847 89.818198)
(xy 145.75636 89.816074)
(xy 145.755058 89.812215)
(xy 145.753265 89.808369)
(xy 145.753694 89.808168)
(xy 145.734032 89.749868)
(xy 145.751041 89.6821)
(xy 145.801989 89.634287)
(xy 145.831841 89.625855)
(xy 145.831476 89.624414)
(xy 145.841435 89.621891)
(xy 145.841437 89.621892)
(xy 145.962922 89.591128)
(xy 146.019492 89.554168)
(xy 146.086378 89.533982)
(xy 146.139715 89.545596)
(xy 146.16524 89.557499)
(xy 146.210821 89.5635)
(xy 146.409178 89.563499)
(xy 146.40918 89.563499)
(xy 146.424372 89.561499)
(xy 146.45476 89.557499)
(xy 146.507597 89.53286)
(xy 146.576671 89.522369)
(xy 146.612401 89.532859)
(xy 146.66524 89.557499)
(xy 146.710821 89.5635)
(xy 146.909178 89.563499)
(xy 146.90918 89.563499)
(xy 146.924372 89.561499)
(xy 146.95476 89.557499)
(xy 147.007597 89.53286)
(xy 147.076671 89.522369)
(xy 147.112401 89.532859)
(xy 147.16524 89.557499)
(xy 147.210821 89.5635)
(xy 147.409178 89.563499)
(xy 147.40918 89.563499)
(xy 147.424372 89.561499)
(xy 147.45476 89.557499)
(xy 147.507597 89.53286)
(xy 147.576671 89.522369)
(xy 147.612401 89.532859)
(xy 147.66524 89.557499)
(xy 147.710821 89.5635)
(xy 147.909178 89.563499)
(xy 147.90918 89.563499)
(xy 147.924372 89.561499)
(xy 147.95476 89.557499)
(xy 148.007597 89.53286)
(xy 148.076671 89.522369)
(xy 148.112401 89.532859)
(xy 148.16524 89.557499)
(xy 148.210821 89.5635)
(xy 148.409178 89.563499)
(xy 148.40918 89.563499)
(xy 148.424372 89.561499)
(xy 148.45476 89.557499)
(xy 148.554799 89.51085)
(xy 148.63285 89.432799)
(xy 148.679499 89.33276)
(xy 148.6855 89.287179)
(xy 148.685499 88.463822)
(xy 148.679499 88.41824)
(xy 148.63285 88.318201)
(xy 148.554799 88.24015)
(xy 148.45476 88.193501)
(xy 148.454758 88.1935)
(xy 148.409188 88.187501)
(xy 148.409185 88.1875)
(xy 148.409179 88.1875)
(xy 148.409172 88.1875)
(xy 148.210819 88.1875)
(xy 148.165243 88.1935)
(xy 148.165238 88.193501)
(xy 148.112403 88.218139)
(xy 148.043325 88.22863)
(xy 148.007595 88.218138)
(xy 147.954759 88.1935)
(xy 147.909188 88.187501)
(xy 147.909185 88.1875)
(xy 147.909179 88.1875)
(xy 147.909172 88.1875)
(xy 147.710819 88.1875)
(xy 147.665243 88.1935)
(xy 147.665238 88.193501)
(xy 147.612403 88.218139)
(xy 147.543325 88.22863)
(xy 147.507595 88.218138)
(xy 147.454759 88.1935)
(xy 147.409188 88.187501)
(xy 147.409185 88.1875)
(xy 147.409179 88.1875)
(xy 147.409172 88.1875)
(xy 147.210819 88.1875)
(xy 147.165243 88.1935)
(xy 147.165238 88.193501)
(xy 147.112403 88.218139)
(xy 147.043325 88.22863)
(xy 147.007595 88.218138)
(xy 146.954759 88.1935)
(xy 146.909188 88.187501)
(xy 146.909185 88.1875)
(xy 146.909179 88.1875)
(xy 146.909172 88.1875)
(xy 146.710819 88.1875)
(xy 146.665243 88.1935)
(xy 146.665238 88.193501)
(xy 146.612403 88.218139)
(xy 146.543325 88.22863)
(xy 146.507595 88.218138)
(xy 146.454759 88.1935)
(xy 146.409188 88.187501)
(xy 146.409185 88.1875)
(xy 146.409179 88.1875)
(xy 146.409172 88.1875)
(xy 146.3345 88.1875)
(xy 146.267461 88.167815)
(xy 146.221706 88.115011)
(xy 146.2105 88.0635)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 146.2105 87.964165)
(xy 146.217511 87.923061)
(xy 146.233644 87.877148)
(xy 146.27444 87.820428)
(xy 146.327431 87.796449)
(xy 146.424872 87.77789)
(xy 146.448072 87.7757)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 148.8105 87.7757)
)
)
(filled_polygon
(layer "F.Cu")
(pts
(xy 143.445139 92.214985)
(xy 143.465781 92.231619)
(xy 143.52605 92.291888)
(xy 143.542175 92.311744)
(xy 143.542996 92.313)
(xy 143.548116 92.320836)
(xy 143.573093 92.340276)
(xy 143.584618 92.350456)
(xy 143.584684 92.350522)
(xy 143.601597 92.362597)
(xy 143.605709 92.365662)
(xy 143.629348 92.384061)
(xy 143.647011 92.397809)
(xy 143.647013 92.397809)
(xy 143.65392 92.401547)
(xy 143.660998 92.405008)
(xy 143.661001 92.40501)
(xy 143.711185 92.41995)
(xy 143.715978 92.421485)
(xy 143.76554 92.4385)
(xy 143.765543 92.438501)
(xy 143.773272 92.43979)
(xy 143.78111 92.440767)
(xy 143.781112 92.440768)
(xy 143.781113 92.440767)
(xy 143.781114 92.440768)
(xy 143.819213 92.439192)
(xy 143.833393 92.438605)
(xy 143.838516 92.4385)
(xy 144.3105 92.4385)
(xy 144.377539 92.458185)
(xy 144.423294 92.510989)
(xy 144.4345 92.562499)
(xy 144.4345 92.66218)
(xy 144.4405 92.707756)
(xy 144.440502 92.707763)
(xy 144.48715 92.807799)
(xy 144.565201 92.88585)
(xy 144.66524 92.932499)
(xy 144.710821 92.9385)
(xy 145.442489 92.938499)
(xy 145.509528 92.958183)
(xy 145.555283 93.010987)
(xy 145.565227 93.080146)
(xy 145.536202 93.143702)
(xy 145.530171 93.150179)
(xy 145.48715 93.1932)
(xy 145.436492 93.301838)
(xy 145.433321 93.300359)
(xy 145.405027 93.344564)
(xy 145.341525 93.373705)
(xy 145.323653 93.375)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 143.07426 93.375)
(xy 143.023849 93.364291)
(xy 142.986626 93.347728)
(xy 142.896288 93.30753)
(xy 142.843042 93.262292)
(xy 142.822706 93.195448)
(xy 142.841737 93.12822)
(xy 142.85902 93.106558)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 142.895476 93.070102)
(xy 142.895478 93.070099)
(xy 142.93463 92.990011)
(xy 142.951982 92.954518)
(xy 142.9629 92.879582)
(xy 142.9629 92.536418)
(xy 142.951982 92.461482)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 142.95037 92.458185)
(xy 142.914133 92.384061)
(xy 142.909096 92.373759)
(xy 142.897337 92.304888)
(xy 142.92468 92.240591)
(xy 142.982444 92.201283)
(xy 143.020497 92.1953)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 143.3781 92.1953)
)
)
(filled_polygon
(layer "F.Cu")
(pts
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 145.167134 87.77789)
(xy 145.167701 87.777998)
(xy 145.167704 87.777999)
(xy 145.287239 87.800767)
(xy 145.349411 87.832648)
(xy 145.378344 87.874516)
(xy 145.399807 87.925563)
(xy 145.4095 87.973624)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 145.4095 88.907024)
(xy 145.424352 89.000799)
(xy 145.42737 89.010086)
(xy 145.424985 89.01086)
(xy 145.4345 89.050487)
(xy 145.4345 89.287174)
(xy 145.440501 89.332761)
(xy 145.443154 89.341863)
(xy 145.442968 89.341917)
(xy 145.449305 89.362343)
(xy 145.449932 89.366102)
(xy 145.449934 89.366108)
(xy 145.449934 89.366109)
(xy 145.449935 89.36611)
(xy 145.509581 89.476326)
(xy 145.509582 89.476327)
(xy 145.515893 89.484435)
(xy 145.513572 89.48624)
(xy 145.541168 89.532168)
(xy 145.539062 89.602006)
(xy 145.499532 89.659619)
(xy 145.43513 89.686714)
(xy 145.421192 89.6875)
(xy 144.710819 89.6875)
(xy 144.665243 89.6935)
(xy 144.665236 89.693502)
(xy 144.5652 89.74015)
(xy 144.48715 89.8182)
(xy 144.4405 89.918241)
(xy 144.434501 89.963811)
(xy 144.4345 89.963827)
(xy 144.4345 90.16218)
(xy 144.4405 90.207756)
(xy 144.440503 90.207766)
(xy 144.465138 90.260596)
(xy 144.47563 90.329673)
(xy 144.465139 90.365404)
(xy 144.4405 90.418243)
(xy 144.434501 90.463811)
(xy 144.4345 90.463827)
(xy 144.4345 90.66218)
(xy 144.4405 90.707756)
(xy 144.440503 90.707766)
(xy 144.465138 90.760596)
(xy 144.47563 90.829673)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 144.465139 90.865403)
(xy 144.456578 90.883764)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 144.4405 90.918243)
(xy 144.434501 90.963811)
(xy 144.4345 90.963827)
(xy 144.4345 91.16218)
(xy 144.4405 91.207756)
(xy 144.440503 91.207766)
(xy 144.465138 91.260596)
(xy 144.47563 91.329673)
(xy 144.465139 91.365403)
(xy 144.443957 91.41083)
(xy 144.4405 91.418243)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 144.434501 91.463811)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 144.4345 91.463821)
(xy 144.4345 91.554015)
(xy 144.434501 91.563499)
(xy 144.414817 91.630538)
(xy 144.362014 91.676294)
(xy 144.310501 91.6875)
(xy 144.056007 91.6875)
(xy 143.988968 91.667815)
(xy 143.943213 91.615011)
(xy 143.940578 91.608801)
(xy 143.93533 91.59543)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 143.906513 91.522002)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 143.904552 91.517005)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 143.838129 91.433715)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 143.819879 91.41083)
(xy 143.819878 91.410829)
(xy 143.819877 91.410828)
(xy 143.819876 91.410827)
(xy 143.707675 91.334329)
(xy 143.707671 91.334327)
(xy 143.577903 91.2943)
(xy 143.577902 91.2943)
(xy 142.460302 91.2943)
(xy 142.457132 91.2943)
(xy 142.42954 91.291191)
(xy 142.426446 91.290485)
(xy 142.426442 91.290484)
(xy 142.382102 91.293808)
(xy 142.380169 91.293953)
(xy 142.370903 91.2943)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 141.634782 91.2943)
(xy 141.603345 91.290249)
(xy 141.370807 91.229303)
(xy 141.310948 91.193265)
(xy 141.282295 91.140791)
(xy 141.221351 90.908254)
(xy 141.2173 90.876817)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 141.2173 88.782365)
(xy 141.236985 88.715326)
(xy 141.253619 88.694684)
(xy 142.136284 87.812019)
(xy 142.197607 87.778534)
(xy 142.223965 87.7757)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 145.143932 87.7757)
New branch for new revision
2024-03-12 11:46:53 +01:00
)
)
(filled_polygon
(layer "F.Cu")
(pts
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 157.092339 83.967185)
(xy 157.138094 84.019989)
(xy 157.1493 84.0715)
(xy 157.1493 108.1663)
(xy 157.129615 108.233339)
(xy 157.076811 108.279094)
(xy 157.0253 108.2903)
(xy 137.8324 108.2903)
(xy 137.765361 108.270615)
(xy 137.719606 108.217811)
(xy 137.7084 108.1663)
(xy 137.7084 101.487)
(xy 139.182222 101.487)
(xy 139.201262 101.643816)
(xy 139.215777 101.682089)
(xy 139.221514 101.708819)
(xy 139.222416 101.708676)
(xy 139.223375 101.714691)
(xy 139.382949 102.323544)
(xy 139.387 102.354981)
(xy 139.387 103.788038)
(xy 139.38622 103.801923)
(xy 139.382229 103.837336)
(xy 139.392855 103.893496)
(xy 139.393632 103.898065)
(xy 139.402152 103.954591)
(xy 139.404662 103.962727)
(xy 139.407476 103.97077)
(xy 139.434188 104.021311)
(xy 139.436276 104.025449)
(xy 139.461074 104.076941)
(xy 139.465862 104.083965)
(xy 139.470931 104.090832)
(xy 139.470934 104.090838)
(xy 139.470938 104.090842)
(xy 139.511346 104.13125)
(xy 139.514563 104.134589)
(xy 139.553447 104.176496)
(xy 139.56071 104.182288)
(xy 139.560189 104.182941)
(xy 139.57243 104.192334)
(xy 140.156055 104.775959)
(xy 140.173341 104.799065)
(xy 140.173618 104.798878)
(xy 140.17704 104.80391)
(xy 140.177042 104.803912)
(xy 140.678208 105.404523)
(xy 140.706045 105.468607)
(xy 140.707 105.483966)
(xy 140.707 106.455678)
(xy 140.721532 106.528735)
(xy 140.721533 106.528739)
(xy 140.721534 106.52874)
(xy 140.776899 106.611601)
(xy 140.85976 106.666966)
(xy 140.859764 106.666967)
(xy 140.932821 106.681499)
(xy 140.932824 106.6815)
(xy 140.932826 106.6815)
(xy 141.982176 106.6815)
(xy 141.982177 106.681499)
(xy 142.05524 106.666966)
(xy 142.138101 106.611601)
(xy 142.193466 106.52874)
(xy 142.207999 106.455678)
(xy 142.707 106.455678)
(xy 142.721532 106.528735)
(xy 142.721533 106.528739)
(xy 142.721534 106.52874)
(xy 142.776899 106.611601)
(xy 142.85976 106.666966)
(xy 142.859764 106.666967)
(xy 142.932821 106.681499)
(xy 142.932824 106.6815)
(xy 142.932826 106.6815)
(xy 143.982176 106.6815)
(xy 143.982177 106.681499)
(xy 144.05524 106.666966)
(xy 144.138101 106.611601)
(xy 144.193466 106.52874)
(xy 144.208 106.455674)
(xy 144.208 103.656326)
(xy 144.208 103.656325)
(xy 144.208 103.656323)
(xy 144.207999 103.656321)
(xy 144.193467 103.583264)
(xy 144.193466 103.58326)
(xy 144.176069 103.557223)
(xy 144.138101 103.500399)
(xy 144.05524 103.445034)
(xy 144.055239 103.445033)
(xy 144.055235 103.445032)
(xy 143.982177 103.4305)
(xy 143.982174 103.4305)
(xy 142.932826 103.4305)
(xy 142.932823 103.4305)
(xy 142.859764 103.445032)
(xy 142.85976 103.445033)
(xy 142.776899 103.500399)
(xy 142.721533 103.58326)
(xy 142.721532 103.583264)
(xy 142.707 103.656321)
(xy 142.707 106.455678)
(xy 142.207999 106.455678)
(xy 142.208 106.455674)
(xy 142.208 103.656326)
(xy 142.208 103.656325)
(xy 142.208 103.656323)
(xy 142.207999 103.656321)
(xy 142.193467 103.583264)
(xy 142.193466 103.58326)
(xy 142.176069 103.557223)
(xy 142.138101 103.500399)
(xy 142.05524 103.445034)
(xy 142.055239 103.445033)
(xy 142.055235 103.445032)
(xy 141.982177 103.4305)
(xy 141.982174 103.4305)
(xy 140.932826 103.4305)
(xy 140.932823 103.4305)
(xy 140.859764 103.445032)
(xy 140.85976 103.445033)
(xy 140.776899 103.500399)
(xy 140.721533 103.58326)
(xy 140.721532 103.583264)
(xy 140.707 103.656321)
(xy 140.707 103.753334)
(xy 140.687315 103.820373)
(xy 140.634511 103.866128)
(xy 140.565353 103.876072)
(xy 140.501797 103.847047)
(xy 140.495319 103.841015)
(xy 140.324319 103.670015)
(xy 140.290834 103.608692)
(xy 140.288 103.582334)
(xy 140.288 102.354981)
(xy 140.292051 102.323544)
(xy 140.451623 101.714696)
(xy 140.451635 101.714571)
(xy 140.451678 101.714384)
(xy 140.452501 101.709747)
(xy 140.452746 101.70979)
(xy 140.45914 101.682307)
(xy 140.472498 101.647085)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 140.473737 101.643818)
(xy 140.492778 101.487)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 140.473737 101.330182)
(xy 140.459465 101.292551)
(xy 140.440199 101.241749)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 140.41772 101.182477)
(xy 140.327983 101.05247)
(xy 140.20974 100.947717)
(xy 140.209738 100.947716)
(xy 140.209737 100.947715)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 140.069865 100.874303)
(xy 139.916486 100.8365)
(xy 139.916485 100.8365)
(xy 139.758515 100.8365)
(xy 139.758514 100.8365)
(xy 139.605134 100.874303)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 139.465262 100.947715)
(xy 139.347016 101.052471)
(xy 139.257281 101.182475)
(xy 139.25728 101.182476)
(xy 139.201262 101.330181)
(xy 139.182222 101.486999)
(xy 139.182222 101.487)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 137.7084 101.487)
(xy 137.7084 96.026)
(xy 139.182222 96.026)
(xy 139.201262 96.182814)
(xy 139.201264 96.182823)
(xy 139.224552 96.244228)
(xy 139.230924 96.267817)
(xy 139.232954 96.28)
(xy 139.44948 96.852788)
(xy 139.453989 96.864714)
(xy 139.462 96.908561)
(xy 139.462 97.570896)
(xy 139.459362 97.596334)
(xy 139.457133 97.606968)
(xy 139.457133 97.60697)
(xy 139.461048 97.638375)
(xy 139.462 97.653713)
(xy 139.462 97.653816)
(xy 139.465418 97.674303)
(xy 139.466157 97.679369)
(xy 139.472634 97.731327)
(xy 139.474873 97.738847)
(xy 139.477435 97.746311)
(xy 139.502327 97.792308)
(xy 139.504671 97.796861)
(xy 139.527672 97.843908)
(xy 139.532242 97.850309)
(xy 139.537081 97.856526)
(xy 139.575608 97.891993)
(xy 139.57928 97.895517)
(xy 140.186827 98.503064)
(xy 140.205099 98.526325)
(xy 140.205898 98.527639)
(xy 140.68213 99.161377)
(xy 140.706668 99.226795)
(xy 140.707 99.235869)
(xy 140.707 100.205678)
(xy 140.721532 100.278735)
(xy 140.721533 100.278739)
(xy 140.721534 100.27874)
(xy 140.776899 100.361601)
(xy 140.8131 100.385789)
(xy 140.85976 100.416966)
(xy 140.859764 100.416967)
(xy 140.932821 100.431499)
(xy 140.932824 100.4315)
(xy 140.932826 100.4315)
(xy 141.982176 100.4315)
(xy 141.982177 100.431499)
(xy 142.05524 100.416966)
(xy 142.138101 100.361601)
(xy 142.193466 100.27874)
(xy 142.208 100.205674)
(xy 142.208 98.25934)
(xy 142.227685 98.192301)
(xy 142.280489 98.146546)
(xy 142.349647 98.136602)
(xy 142.413203 98.165627)
(xy 142.449917 98.22098)
(xy 142.700918 98.992562)
(xy 142.707 99.030921)
(xy 142.707 100.205678)
(xy 142.721532 100.278735)
(xy 142.721533 100.278739)
(xy 142.721534 100.27874)
(xy 142.776899 100.361601)
(xy 142.8131 100.385789)
(xy 142.85976 100.416966)
(xy 142.859764 100.416967)
(xy 142.932821 100.431499)
(xy 142.932824 100.4315)
(xy 142.932826 100.4315)
(xy 143.982176 100.4315)
(xy 143.982177 100.431499)
(xy 144.05524 100.416966)
(xy 144.138101 100.361601)
(xy 144.193466 100.27874)
(xy 144.208 100.205674)
(xy 144.208 97.406326)
(xy 144.208 97.406323)
(xy 144.207999 97.406321)
(xy 144.193467 97.333264)
(xy 144.193466 97.33326)
(xy 144.16533 97.291151)
(xy 144.138101 97.250399)
(xy 144.062099 97.199617)
(xy 144.055239 97.195033)
(xy 144.055235 97.195032)
(xy 143.982177 97.1805)
(xy 143.982174 97.1805)
(xy 143.185154 97.1805)
(xy 143.158075 97.177507)
(xy 143.148459 97.175355)
(xy 143.148455 97.175354)
(xy 142.888946 97.16917)
(xy 142.822394 97.147894)
(xy 142.77791 97.094014)
(xy 142.7679 97.045205)
(xy 142.7679 94.364673)
(xy 142.780078 94.311084)
(xy 142.805466 94.258108)
(xy 142.815267 94.237657)
(xy 142.86199 94.18571)
(xy 142.889545 94.173068)
(xy 143.019429 94.131816)
(xy 143.056961 94.126)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 143.166065 94.126)
(xy 143.233104 94.145685)
(xy 143.278859 94.198489)
(xy 143.288803 94.267647)
(xy 143.282007 94.293971)
(xy 143.229363 94.432781)
(xy 143.210322 94.589599)
(xy 143.210322 94.5896)
(xy 143.229362 94.746418)
(xy 143.28538 94.894123)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 143.285381 94.894124)
(xy 143.375118 95.024132)
(xy 143.37755 95.026877)
(xy 143.387316 95.039443)
(xy 143.47594 95.169964)
(xy 143.496401 95.224278)
(xy 143.500732 95.259022)
(xy 143.502971 95.266541)
(xy 143.505535 95.27401)
(xy 143.530453 95.320054)
(xy 143.532766 95.324548)
(xy 143.555774 95.371611)
(xy 143.555775 95.371612)
(xy 143.555776 95.371614)
(xy 143.560329 95.377991)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 143.565178 95.384221)
(xy 143.565181 95.384226)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 143.582247 95.399936)
(xy 143.595661 95.412285)
(xy 143.628067 95.460744)
(xy 143.689477 95.627861)
(xy 143.69109 95.632249)
(xy 143.6987 95.675019)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 143.6987 95.725582)
(xy 143.709618 95.800518)
(xy 143.709618 95.800519)
(xy 143.709619 95.800521)
(xy 143.766121 95.916099)
(xy 143.766123 95.916102)
(xy 143.857097 96.007076)
(xy 143.8571 96.007078)
(xy 143.967856 96.061222)
(xy 143.972682 96.063582)
(xy 144.047618 96.0745)
(xy 144.047623 96.0745)
(xy 144.21641 96.0745)
(xy 144.283449 96.094185)
(xy 144.329204 96.146989)
(xy 144.339148 96.216147)
(xy 144.332352 96.242471)
(xy 144.281263 96.377181)
(xy 144.262222 96.533999)
(xy 144.262222 96.534)
(xy 144.281262 96.690818)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 144.332795 96.826696)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 144.33728 96.838523)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 144.427017 96.96853)
(xy 144.54526 97.073283)
(xy 144.545262 97.073284)
(xy 144.681074 97.144565)
(xy 144.731287 97.19315)
(xy 144.747261 97.261169)
(xy 144.73217 97.31399)
(xy 144.724728 97.327559)
(xy 144.724135 97.327234)
(xy 144.723623 97.328215)
(xy 144.721533 97.333261)
(xy 144.705811 97.412301)
(xy 144.705661 97.412271)
(xy 144.70563 97.412453)
(xy 144.704942 97.417275)
(xy 144.704552 97.426215)
(xy 144.704553 97.42622)
(xy 144.705329 97.431262)
(xy 144.705556 97.432732)
(xy 144.707 97.451602)
(xy 144.707 100.205678)
(xy 144.721532 100.278735)
(xy 144.721533 100.278739)
(xy 144.721534 100.27874)
(xy 144.776899 100.361601)
(xy 144.8131 100.385789)
(xy 144.85976 100.416966)
(xy 144.859764 100.416967)
(xy 144.932821 100.431499)
(xy 144.932824 100.4315)
(xy 145.9569 100.4315)
(xy 146.023939 100.451185)
(xy 146.069694 100.503989)
(xy 146.0809 100.5555)
(xy 146.0809 100.732699)
(xy 146.061215 100.799738)
(xy 146.044581 100.82038)
(xy 145.228608 101.636352)
(xy 145.208754 101.652476)
(xy 145.199665 101.658414)
(xy 145.199664 101.658415)
(xy 145.18022 101.683396)
(xy 145.170074 101.694888)
(xy 145.169983 101.694979)
(xy 145.169974 101.694989)
(xy 145.157902 101.711897)
(xy 145.154841 101.716003)
(xy 145.122692 101.757308)
(xy 145.118947 101.764229)
(xy 145.115488 101.771304)
(xy 145.100557 101.821455)
(xy 145.098995 101.826331)
(xy 145.082 101.875838)
(xy 145.080706 101.883592)
(xy 145.079731 101.891411)
(xy 145.081894 101.943691)
(xy 145.082 101.948816)
(xy 145.082 103.047832)
(xy 145.062315 103.114871)
(xy 145.0572 103.122232)
(xy 144.756906 103.522624)
(xy 144.756891 103.522645)
(xy 144.742156 103.544569)
(xy 144.742139 103.544595)
(xy 144.740914 103.546639)
(xy 144.724952 103.576678)
(xy 144.724385 103.576376)
(xy 144.721533 103.583262)
(xy 144.706015 103.661275)
(xy 144.704828 103.666623)
(xy 144.704809 103.6667)
(xy 144.704807 103.666712)
(xy 144.704434 103.675132)
(xy 144.704409 103.675644)
(xy 144.70441 103.675666)
(xy 144.705567 103.683207)
(xy 144.707 103.702005)
(xy 144.707 106.455678)
(xy 144.721532 106.528735)
(xy 144.721533 106.528739)
(xy 144.721534 106.52874)
(xy 144.776899 106.611601)
(xy 144.85976 106.666966)
(xy 144.859764 106.666967)
(xy 144.932821 106.681499)
(xy 144.932824 106.6815)
(xy 144.932826 106.6815)
(xy 145.982176 106.6815)
(xy 145.982177 106.681499)
(xy 146.05524 106.666966)
(xy 146.138101 106.611601)
(xy 146.193466 106.52874)
(xy 146.207999 106.455678)
(xy 146.707 106.455678)
(xy 146.721532 106.528735)
(xy 146.721533 106.528739)
(xy 146.721534 106.52874)
(xy 146.776899 106.611601)
(xy 146.85976 106.666966)
(xy 146.859764 106.666967)
(xy 146.932821 106.681499)
(xy 146.932824 106.6815)
(xy 146.932826 106.6815)
(xy 147.982176 106.6815)
(xy 147.982177 106.681499)
(xy 148.05524 106.666966)
(xy 148.138101 106.611601)
(xy 148.193466 106.52874)
(xy 148.207999 106.455678)
(xy 148.707 106.455678)
(xy 148.721532 106.528735)
(xy 148.721533 106.528739)
(xy 148.721534 106.52874)
(xy 148.776899 106.611601)
(xy 148.85976 106.666966)
(xy 148.859764 106.666967)
(xy 148.932821 106.681499)
(xy 148.932824 106.6815)
(xy 148.932826 106.6815)
(xy 149.982176 106.6815)
(xy 149.982177 106.681499)
(xy 150.05524 106.666966)
(xy 150.138101 106.611601)
(xy 150.193466 106.52874)
(xy 150.208 106.455674)
(xy 150.208 103.656326)
(xy 150.208 103.656325)
(xy 150.208 103.656323)
(xy 150.207999 103.656321)
(xy 150.193467 103.583264)
(xy 150.193466 103.58326)
(xy 150.176069 103.557223)
(xy 150.138101 103.500399)
(xy 150.05524 103.445034)
(xy 150.055239 103.445033)
(xy 150.055235 103.445032)
(xy 149.982177 103.4305)
(xy 149.982174 103.4305)
(xy 148.932826 103.4305)
(xy 148.932823 103.4305)
(xy 148.859764 103.445032)
(xy 148.85976 103.445033)
(xy 148.776899 103.500399)
(xy 148.721533 103.58326)
(xy 148.721532 103.583264)
(xy 148.707 103.656321)
(xy 148.707 106.455678)
(xy 148.207999 106.455678)
(xy 148.208 106.455674)
(xy 148.208 103.656326)
(xy 148.208 103.656325)
(xy 148.208 103.656323)
(xy 148.207999 103.656321)
(xy 148.193467 103.583264)
(xy 148.193466 103.58326)
(xy 148.176069 103.557223)
(xy 148.138101 103.500399)
(xy 148.05524 103.445034)
(xy 148.055239 103.445033)
(xy 148.055235 103.445032)
(xy 147.982177 103.4305)
(xy 147.982174 103.4305)
(xy 146.932826 103.4305)
(xy 146.932823 103.4305)
(xy 146.859764 103.445032)
(xy 146.85976 103.445033)
(xy 146.776899 103.500399)
(xy 146.721533 103.58326)
(xy 146.721532 103.583264)
(xy 146.707 103.656321)
(xy 146.707 106.455678)
(xy 146.207999 106.455678)
(xy 146.208 106.455674)
(xy 146.208 103.737133)
(xy 146.208849 103.728463)
(xy 146.208318 103.728426)
(xy 146.208852 103.720758)
(xy 146.208183 103.708467)
(xy 146.208 103.701727)
(xy 146.208 103.656325)
(xy 146.206064 103.646595)
(xy 146.203863 103.629135)
(xy 146.203432 103.621214)
(xy 146.203432 103.621212)
(xy 146.20121 103.612537)
(xy 146.201206 103.612524)
(xy 146.201205 103.612523)
(xy 146.199853 103.608128)
(xy 146.199934 103.608102)
(xy 146.19516 103.591775)
(xy 146.193467 103.583262)
(xy 146.184529 103.569885)
(xy 146.17606 103.55721)
(xy 146.167369 103.541964)
(xy 146.1581 103.522634)
(xy 146.018587 103.336616)
(xy 145.8578 103.122232)
(xy 145.833324 103.056789)
(xy 145.833 103.047832)
(xy 145.833 102.145399)
(xy 145.852685 102.07836)
(xy 145.869319 102.057718)
(xy 146.276835 101.650202)
(xy 146.685292 101.241744)
(xy 146.705141 101.225625)
(xy 146.714236 101.219684)
(xy 146.733672 101.19471)
(xy 146.74385 101.183187)
(xy 146.74392 101.183118)
(xy 146.756007 101.166186)
(xy 146.759066 101.162085)
(xy 146.772466 101.144868)
(xy 146.791209 101.120789)
(xy 146.791211 101.120782)
(xy 146.794947 101.11388)
(xy 146.798403 101.106807)
(xy 146.79841 101.106799)
(xy 146.813355 101.056595)
(xy 146.814883 101.051824)
(xy 146.8319 101.00226)
(xy 146.8319 101.002256)
(xy 146.83319 100.994524)
(xy 146.834168 100.986685)
(xy 146.832599 100.94875)
(xy 146.849496 100.880954)
(xy 146.900364 100.833056)
(xy 146.969052 100.820263)
(xy 147.033753 100.846636)
(xy 147.073925 100.903803)
(xy 147.07954 100.928285)
(xy 147.081047 100.940373)
(xy 147.082 100.955713)
(xy 147.082 100.955816)
(xy 147.085418 100.976303)
(xy 147.086157 100.981369)
(xy 147.092634 101.033327)
(xy 147.094873 101.040847)
(xy 147.097435 101.048311)
(xy 147.122327 101.094308)
(xy 147.124671 101.098861)
(xy 147.147672 101.145908)
(xy 147.152242 101.152309)
(xy 147.157081 101.158526)
(xy 147.195608 101.193993)
(xy 147.19928 101.197517)
(xy 147.576649 101.574886)
(xy 147.592777 101.594745)
(xy 147.598716 101.603836)
(xy 147.601532 101.606028)
(xy 147.623693 101.623276)
(xy 147.635212 101.633449)
(xy 147.635282 101.633519)
(xy 147.652189 101.64559)
(xy 147.656301 101.648656)
(xy 147.69761 101.680809)
(xy 147.704504 101.684539)
(xy 147.711598 101.688008)
(xy 147.711601 101.68801)
(xy 147.761785 101.70295)
(xy 147.766578 101.704485)
(xy 147.81614 101.7215)
(xy 147.816143 101.721501)
(xy 147.823872 101.72279)
(xy 147.83171 101.723767)
(xy 147.831712 101.723768)
(xy 147.831713 101.723767)
(xy 147.831714 101.723768)
(xy 147.869813 101.722192)
(xy 147.883993 101.721605)
(xy 147.889116 101.7215)
(xy 148.030196 101.7215)
(xy 148.055641 101.724139)
(xy 148.058724 101.724785)
(xy 148.066268 101.726367)
(xy 148.097676 101.722451)
(xy 148.113014 101.7215)
(xy 148.113112 101.7215)
(xy 148.113114 101.7215)
(xy 148.133643 101.718073)
(xy 148.138673 101.717341)
(xy 148.190626 101.710866)
(xy 148.190628 101.710864)
(xy 148.198141 101.708628)
(xy 148.205606 101.706066)
(xy 148.205606 101.706065)
(xy 148.20561 101.706065)
(xy 148.247498 101.683396)
(xy 148.251636 101.681157)
(xy 148.256193 101.678812)
(xy 148.271102 101.671522)
(xy 148.303211 101.655826)
(xy 148.303213 101.655823)
(xy 148.3096 101.651264)
(xy 148.31582 101.646421)
(xy 148.315826 101.646419)
(xy 148.351293 101.60789)
(xy 148.354795 101.60424)
(xy 148.666489 101.292546)
(xy 148.686346 101.276422)
(xy 148.695436 101.270484)
(xy 148.714871 101.245512)
(xy 148.725056 101.233981)
(xy 148.725056 101.23398)
(xy 148.725119 101.233918)
(xy 148.73723 101.216953)
(xy 148.740227 101.212934)
(xy 148.772409 101.171589)
(xy 148.772411 101.171581)
(xy 148.776147 101.164678)
(xy 148.779606 101.157603)
(xy 148.77961 101.157599)
(xy 148.794542 101.107441)
(xy 148.796086 101.102618)
(xy 148.8131 101.05306)
(xy 148.8131 101.053058)
(xy 148.813101 101.053056)
(xy 148.814391 101.045324)
(xy 148.815368 101.037486)
(xy 148.813206 100.985207)
(xy 148.8131 100.980083)
(xy 148.8131 100.5555)
(xy 148.832785 100.488461)
(xy 148.885589 100.442706)
(xy 148.9371 100.4315)
(xy 149.982176 100.4315)
(xy 149.982177 100.431499)
(xy 150.05524 100.416966)
(xy 150.138101 100.361601)
(xy 150.193466 100.27874)
(xy 150.207999 100.205678)
(xy 150.707 100.205678)
(xy 150.721532 100.278735)
(xy 150.721533 100.278739)
(xy 150.721534 100.27874)
(xy 150.776899 100.361601)
(xy 150.8131 100.385789)
(xy 150.85976 100.416966)
(xy 150.859764 100.416967)
(xy 150.932821 100.431499)
(xy 150.932824 100.4315)
(xy 150.932826 100.4315)
(xy 151.982176 100.4315)
(xy 151.982177 100.431499)
(xy 152.05524 100.416966)
(xy 152.138101 100.361601)
(xy 152.193466 100.27874)
(xy 152.208 100.205674)
(xy 152.208 97.406326)
(xy 152.208 97.406323)
(xy 152.207999 97.406321)
(xy 152.193467 97.333264)
(xy 152.193466 97.33326)
(xy 152.16533 97.291151)
(xy 152.138101 97.250399)
(xy 152.062099 97.199617)
(xy 152.055239 97.195033)
(xy 152.055235 97.195032)
(xy 151.982177 97.1805)
(xy 151.982174 97.1805)
(xy 150.932826 97.1805)
(xy 150.932823 97.1805)
(xy 150.859764 97.195032)
(xy 150.85976 97.195033)
(xy 150.776899 97.250399)
(xy 150.721533 97.33326)
(xy 150.721532 97.333264)
(xy 150.707 97.406321)
(xy 150.707 100.205678)
(xy 150.207999 100.205678)
(xy 150.208 100.205674)
(xy 150.208 97.406326)
(xy 150.208 97.406323)
(xy 150.207999 97.406321)
(xy 150.193467 97.333264)
(xy 150.193466 97.33326)
(xy 150.16533 97.291151)
(xy 150.138101 97.250399)
(xy 150.062099 97.199617)
(xy 150.055239 97.195033)
(xy 150.055235 97.195032)
(xy 149.982177 97.1805)
(xy 149.982174 97.1805)
(xy 148.9371 97.1805)
(xy 148.870061 97.160815)
(xy 148.824306 97.108011)
(xy 148.8131 97.0565)
(xy 148.8131 95.78559)
(xy 148.815739 95.760145)
(xy 148.816731 95.755413)
(xy 148.817967 95.749518)
(xy 148.814052 95.718111)
(xy 148.8131 95.702773)
(xy 148.8131 95.702676)
(xy 148.813099 95.702664)
(xy 148.810061 95.684466)
(xy 148.809676 95.682156)
(xy 148.808939 95.677102)
(xy 148.808679 95.675019)
(xy 148.802465 95.625161)
(xy 148.800217 95.617614)
(xy 148.797666 95.61018)
(xy 148.797665 95.610178)
(xy 148.797665 95.610177)
(xy 148.785515 95.587726)
(xy 148.770921 95.5194)
(xy 148.795584 95.454028)
(xy 148.851674 95.412367)
(xy 148.921384 95.407645)
(xy 148.982252 95.44103)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 149.02011 95.478888)
(xy 149.036235 95.498744)
(xy 149.038217 95.501777)
(xy 149.042176 95.507836)
(xy 149.067153 95.527276)
(xy 149.078678 95.537456)
(xy 149.078744 95.537522)
(xy 149.095657 95.549597)
(xy 149.099769 95.552662)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 149.111646 95.561906)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 149.141071 95.584809)
(xy 149.141073 95.584809)
(xy 149.14798 95.588547)
(xy 149.155058 95.592008)
(xy 149.155061 95.59201)
(xy 149.205245 95.60695)
(xy 149.210038 95.608485)
(xy 149.2596 95.6255)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 149.259603 95.6255)
(xy 149.26648 95.627861)
(xy 149.281457 95.632056)
(xy 149.584341 95.753367)
(xy 149.588283 95.754429)
(xy 149.59193 95.755413)
(xy 149.615951 95.764655)
(xy 149.618622 95.766016)
(xy 149.618629 95.766018)
(xy 149.646364 95.77041)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 149.710065 95.7805)
(xy 150.111534 95.780499)
(xy 150.111539 95.780499)
(xy 150.111539 95.780498)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 150.160595 95.772729)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 150.20297 95.766018)
(xy 150.202972 95.766017)
(xy 150.202975 95.766017)
(xy 150.313191 95.709859)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 150.344694 95.678354)
(xy 150.362896 95.66333)
(xy 150.368509 95.659534)
(xy 150.399646 95.644321)
(xy 150.401701 95.643654)
(xy 150.420615 95.639112)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 150.442504 95.635646)
(xy 150.462244 95.625586)
(xy 150.480211 95.618144)
(xy 150.50129 95.611296)
(xy 150.501299 95.611289)
(xy 150.502736 95.610558)
(xy 150.504687 95.610191)
(xy 150.510574 95.608279)
(xy 150.51082 95.609039)
(xy 150.571405 95.597657)
(xy 150.636147 95.62393)
(xy 150.676407 95.681033)
(xy 150.682134 95.735985)
(xy 150.673269 95.808999)
(xy 150.673269 95.809)
(xy 150.692309 95.965818)
(xy 150.736169 96.081465)
(xy 150.748327 96.113523)
(xy 150.838064 96.24353)
(xy 150.956307 96.348283)
(xy 150.956309 96.348284)
(xy 151.096181 96.421696)
(xy 151.249561 96.4595)
(xy 151.249562 96.4595)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 151.310996 96.4595)
(xy 151.331505 96.461207)
(xy 151.348279 96.464021)
(xy 152.027159 96.443526)
(xy 152.03733 96.441261)
(xy 152.064272 96.4383)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 154.024596 96.4383)
(xy 154.050041 96.440939)
(xy 154.053124 96.441585)
(xy 154.060668 96.443167)
(xy 154.092076 96.439251)
(xy 154.107414 96.4383)
(xy 154.107512 96.4383)
(xy 154.107514 96.4383)
(xy 154.128043 96.434873)
(xy 154.133073 96.434141)
(xy 154.185026 96.427666)
(xy 154.185028 96.427664)
(xy 154.192541 96.425428)
(xy 154.200006 96.422866)
(xy 154.200006 96.422865)
(xy 154.20001 96.422865)
(xy 154.246036 96.397957)
(xy 154.250593 96.395612)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 154.265502 96.388322)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 154.297611 96.372626)
(xy 154.297613 96.372623)
(xy 154.303994 96.368068)
(xy 154.310219 96.363222)
(xy 154.310226 96.363219)
(xy 154.345691 96.324692)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 154.349193 96.321042)
(xy 154.452402 96.217834)
(xy 154.513724 96.184351)
(xy 154.583416 96.189335)
(xy 154.584067 96.18958)
(xy 154.59543 96.193913)
(xy 154.651056 96.236187)
(xy 154.663072 96.256181)
(xy 154.704721 96.343083)
(xy 154.7169 96.396674)
(xy 154.7169 97.379899)
(xy 154.697215 97.446938)
(xy 154.680581 97.46758)
(xy 154.419681 97.72848)
(xy 154.358358 97.761965)
(xy 154.288666 97.756981)
(xy 154.232733 97.715109)
(xy 154.208316 97.649645)
(xy 154.208 97.640799)
(xy 154.208 97.406323)
(xy 154.207999 97.406321)
(xy 154.193467 97.333264)
(xy 154.193466 97.33326)
(xy 154.16533 97.291151)
(xy 154.138101 97.250399)
(xy 154.062099 97.199617)
(xy 154.055239 97.195033)
(xy 154.055235 97.195032)
(xy 153.982177 97.1805)
(xy 153.982174 97.1805)
(xy 152.932826 97.1805)
(xy 152.932823 97.1805)
(xy 152.859764 97.195032)
(xy 152.85976 97.195033)
(xy 152.776899 97.250399)
(xy 152.721533 97.33326)
(xy 152.721532 97.333264)
(xy 152.707 97.406321)
(xy 152.707 100.205678)
(xy 152.721532 100.278735)
(xy 152.721533 100.278739)
(xy 152.721534 100.27874)
(xy 152.776899 100.361601)
(xy 152.8131 100.385789)
(xy 152.85976 100.416966)
(xy 152.859764 100.416967)
(xy 152.932821 100.431499)
(xy 152.932824 100.4315)
(xy 152.932826 100.4315)
(xy 153.982176 100.4315)
(xy 153.982177 100.431499)
(xy 154.05524 100.416966)
(xy 154.138101 100.361601)
(xy 154.193466 100.27874)
(xy 154.208 100.205674)
(xy 154.208 99.22867)
(xy 154.227685 99.161631)
(xy 154.231989 99.155364)
(xy 154.70491 98.51035)
(xy 154.704918 98.510333)
(xy 154.705441 98.509489)
(xy 154.706795 98.507777)
(xy 154.707812 98.506391)
(xy 154.707863 98.506428)
(xy 154.723244 98.486991)
(xy 155.321289 97.888946)
(xy 155.341146 97.872822)
(xy 155.350236 97.866884)
(xy 155.369671 97.841912)
(xy 155.379856 97.830381)
(xy 155.379856 97.83038)
(xy 155.379919 97.830318)
(xy 155.39203 97.813353)
(xy 155.395027 97.809334)
(xy 155.427209 97.767989)
(xy 155.427211 97.767981)
(xy 155.430947 97.761078)
(xy 155.434406 97.754003)
(xy 155.43441 97.753999)
(xy 155.449342 97.703841)
(xy 155.450886 97.699018)
(xy 155.4679 97.64946)
(xy 155.4679 97.649458)
(xy 155.467901 97.649456)
(xy 155.469191 97.641724)
(xy 155.470168 97.633886)
(xy 155.468006 97.581607)
(xy 155.4679 97.576483)
(xy 155.4679 96.396673)
(xy 155.480078 96.343083)
(xy 155.56809 96.159436)
(xy 155.592234 96.125344)
(xy 155.595473 96.122105)
(xy 155.595473 96.122104)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 155.595476 96.122102)
(xy 155.651982 96.006518)
(xy 155.6629 95.931582)
(xy 155.6629 95.588418)
(xy 155.651982 95.513482)
(xy 155.638897 95.486717)
(xy 155.595478 95.3979)
(xy 155.595476 95.397897)
(xy 155.53526 95.337681)
(xy 155.501775 95.276358)
(xy 155.506759 95.206666)
(xy 155.53526 95.162319)
(xy 155.595476 95.102102)
(xy 155.595478 95.102099)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 155.631065 95.029304)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 155.651982 94.986518)
(xy 155.6629 94.911582)
(xy 155.6629 94.568418)
(xy 155.651982 94.493482)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 155.623467 94.435155)
(xy 155.602324 94.391906)
(xy 155.592915 94.365395)
(xy 155.546091 94.16301)
(xy 155.5429 94.13506)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 155.5429 92.384061)
(xy 155.54368 92.370176)
(xy 155.54767 92.334766)
(xy 155.545034 92.320836)
(xy 155.537033 92.278553)
(xy 155.536264 92.274019)
(xy 155.527748 92.217515)
(xy 155.527748 92.217513)
(xy 155.527746 92.217509)
(xy 155.525236 92.209371)
(xy 155.522424 92.201334)
(xy 155.522423 92.201328)
(xy 155.495685 92.150741)
(xy 155.493623 92.146654)
(xy 155.468825 92.095158)
(xy 155.468823 92.095156)
(xy 155.468823 92.095155)
(xy 155.464042 92.088142)
(xy 155.458966 92.081265)
(xy 155.458965 92.081262)
(xy 155.418565 92.040862)
(xy 155.415347 92.037521)
(xy 155.37646 91.995609)
(xy 155.369192 91.989814)
(xy 155.369712 91.989161)
(xy 155.357467 91.979764)
(xy 155.106168 91.728465)
(xy 155.096902 91.718097)
(xy 155.088663 91.707766)
(xy 155.074679 91.69023)
(xy 155.074678 91.690229)
(xy 155.074677 91.690228)
(xy 155.04915 91.672824)
(xy 155.027433 91.658018)
(xy 155.023669 91.655347)
(xy 154.977686 91.621409)
(xy 154.970097 91.617398)
(xy 154.962475 91.613728)
(xy 154.907849 91.596879)
(xy 154.903444 91.59543)
(xy 154.849495 91.576552)
(xy 154.841126 91.574968)
(xy 154.832704 91.5737)
(xy 154.832702 91.5737)
(xy 154.775538 91.5737)
(xy 154.770901 91.573613)
(xy 154.768885 91.573537)
(xy 154.713789 91.571475)
(xy 154.704556 91.572516)
(xy 154.704462 91.571686)
(xy 154.689164 91.5737)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 154.3795 91.5737)
(xy 154.312461 91.554015)
(xy 154.266706 91.501211)
(xy 154.256535 91.433715)
(xy 154.281185 91.244093)
(xy 154.281184 91.244093)
(xy 154.281188 91.24407)
(xy 154.282951 91.197409)
(xy 154.282722 91.193152)
(xy 154.280609 91.17873)
(xy 154.279299 91.160754)
(xy 154.279299 90.832867)
(xy 154.278916 90.828002)
(xy 154.279167 90.827982)
(xy 154.278211 90.815202)
(xy 154.278272 90.80784)
(xy 154.212746 90.463821)
(xy 154.20149 90.404725)
(xy 154.1993 90.381524)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 154.1993 88.299861)
(xy 154.20008 88.285976)
(xy 154.200556 88.281757)
(xy 154.20407 88.250565)
(xy 154.193432 88.194341)
(xy 154.19267 88.189853)
(xy 154.184148 88.133313)
(xy 154.184147 88.133311)
(xy 154.184147 88.133309)
(xy 154.181629 88.125145)
(xy 154.178823 88.117124)
(xy 154.152106 88.066578)
(xy 154.150013 88.062433)
(xy 154.125225 88.010958)
(xy 154.12042 88.00391)
(xy 154.115367 87.997065)
(xy 154.115366 87.997062)
(xy 154.074952 87.956648)
(xy 154.071735 87.953308)
(xy 154.032857 87.911407)
(xy 154.02559 87.905612)
(xy 154.02611 87.904959)
(xy 154.01387 87.895566)
(xy 153.147768 87.029465)
(xy 153.138502 87.019097)
(xy 153.125068 87.002251)
(xy 153.116279 86.99123)
(xy 153.116278 86.991229)
(xy 153.116277 86.991228)
(xy 153.09075 86.973824)
(xy 153.069033 86.959018)
(xy 153.065269 86.956347)
(xy 153.019286 86.922409)
(xy 153.011697 86.918398)
(xy 153.004075 86.914728)
(xy 152.949449 86.897879)
(xy 152.945044 86.89643)
(xy 152.94146 86.895176)
(xy 152.933456 86.892375)
(xy 152.891095 86.877552)
(xy 152.882726 86.875968)
(xy 152.874304 86.8747)
(xy 152.874302 86.8747)
(xy 152.817138 86.8747)
(xy 152.812501 86.874613)
(xy 152.810485 86.874537)
(xy 152.755389 86.872475)
(xy 152.746156 86.873516)
(xy 152.746062 86.872686)
(xy 152.730764 86.8747)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 146.448068 86.8747)
(xy 146.424866 86.87251)
(xy 146.424297 86.872401)
(xy 146.424296 86.872401)
(xy 146.275894 86.844133)
(xy 146.139944 86.818238)
(xy 146.139929 86.818234)
(xy 146.021765 86.795727)
(xy 145.994752 86.793508)
(xy 145.967746 86.79129)
(xy 145.96774 86.79129)
(xy 145.967739 86.79129)
(xy 145.962822 86.791409)
(xy 145.962809 86.791409)
(xy 145.962808 86.79141)
(xy 145.962806 86.79141)
(xy 145.962796 86.791411)
(xy 145.945828 86.793642)
(xy 145.929667 86.7947)
(xy 145.595264 86.7947)
(xy 145.590409 86.795083)
(xy 145.590389 86.794836)
(xy 145.577631 86.795786)
(xy 145.570242 86.795726)
(xy 145.570236 86.795727)
(xy 145.350573 86.837567)
(xy 145.167702 86.8724)
(xy 145.167699 86.872401)
(xy 145.167127 86.87251)
(xy 145.143925 86.8747)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 142.018262 86.8747)
(xy 142.004379 86.87392)
(xy 141.99937 86.873355)
(xy 141.968963 86.869929)
(xy 141.91281 86.880554)
(xy 141.908241 86.881331)
(xy 141.851715 86.889851)
(xy 141.843532 86.892375)
(xy 141.835529 86.895176)
(xy 141.784985 86.921889)
(xy 141.780848 86.923977)
(xy 141.729358 86.948773)
(xy 141.722338 86.953559)
(xy 141.71546 86.958635)
(xy 141.675058 86.999037)
(xy 141.671722 87.002251)
(xy 141.629804 87.041146)
(xy 141.624013 87.048408)
(xy 141.623362 87.047888)
(xy 141.613967 87.060128)
(xy 140.471063 88.203032)
(xy 140.460698 88.212295)
(xy 140.432833 88.234517)
(xy 140.43283 88.234521)
(xy 140.400623 88.281757)
(xy 140.397944 88.285532)
(xy 140.364006 88.331518)
(xy 140.360016 88.339067)
(xy 140.356328 88.346725)
(xy 140.339473 88.401367)
(xy 140.338025 88.405768)
(xy 140.319153 88.459704)
(xy 140.317571 88.468059)
(xy 140.3163 88.4765)
(xy 140.3163 88.53366)
(xy 140.316213 88.538297)
(xy 140.314075 88.595409)
(xy 140.315116 88.604643)
(xy 140.314285 88.604736)
(xy 140.3163 88.620035)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 140.3163 90.876817)
(xy 140.312249 90.908254)
(xy 140.152676 91.517106)
(xy 140.152674 91.517117)
(xy 140.152662 91.517245)
(xy 140.152617 91.517435)
(xy 140.1518 91.522046)
(xy 140.151555 91.522002)
(xy 140.145161 91.549487)
(xy 140.130562 91.587982)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 140.111522 91.744799)
(xy 140.111522 91.7448)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 140.130562 91.901618)
(xy 140.182104 92.037521)
(xy 140.18658 92.049323)
(xy 140.276317 92.17933)
(xy 140.39456 92.284083)
(xy 140.394562 92.284084)
(xy 140.534434 92.357496)
(xy 140.687814 92.3953)
(xy 140.687815 92.3953)
(xy 140.845784 92.3953)
(xy 140.845785 92.3953)
(xy 140.986302 92.360665)
(xy 140.993066 92.359296)
(xy 140.994487 92.358923)
(xy 140.994496 92.358923)
(xy 141.603344 92.19935)
(xy 141.634781 92.1953)
(xy 141.764301 92.1953)
(xy 141.83134 92.214985)
(xy 141.877095 92.267789)
(xy 141.887039 92.336947)
(xy 141.875702 92.37376)
(xy 141.832818 92.46148)
(xy 141.832477 92.463821)
(xy 141.8219 92.536418)
(xy 141.8219 92.879582)
(xy 141.832818 92.954518)
(xy 141.832818 92.954519)
(xy 141.832819 92.954521)
(xy 141.889321 93.070099)
(xy 141.889323 93.070102)
(xy 141.94954 93.130319)
(xy 141.983025 93.191642)
(xy 141.978041 93.261334)
(xy 141.94954 93.305681)
(xy 141.889323 93.365897)
(xy 141.889321 93.3659)
(xy 141.832819 93.481478)
(xy 141.832818 93.48148)
(xy 141.832818 93.481482)
(xy 141.8219 93.556418)
(xy 141.8219 93.899582)
(xy 141.832818 93.974518)
(xy 141.832818 93.974519)
(xy 141.832819 93.974521)
(xy 141.889321 94.090099)
(xy 141.889323 94.090102)
(xy 141.892566 94.093345)
(xy 141.916706 94.127435)
(xy 142.004721 94.311083)
(xy 142.0169 94.364674)
(xy 142.0169 97.0565)
(xy 141.997215 97.123539)
(xy 141.944411 97.169294)
(xy 141.8929 97.1805)
(xy 140.932823 97.1805)
(xy 140.859764 97.195032)
(xy 140.85976 97.195033)
(xy 140.776899 97.250399)
(xy 140.721533 97.33326)
(xy 140.721532 97.333264)
(xy 140.707 97.406321)
(xy 140.707 97.6618)
(xy 140.687315 97.728839)
(xy 140.634511 97.774594)
(xy 140.565353 97.784538)
(xy 140.501797 97.755513)
(xy 140.495319 97.749481)
(xy 140.249319 97.503481)
(xy 140.215834 97.442158)
(xy 140.213 97.4158)
(xy 140.213 96.90856)
(xy 140.221011 96.864714)
(xy 140.298313 96.660223)
(xy 140.442045 96.279999)
(xy 140.444452 96.266259)
(xy 140.450647 96.2437)
(xy 140.473737 96.182818)
(xy 140.492778 96.026)
(xy 140.490481 96.007078)
(xy 140.473737 95.869181)
(xy 140.440104 95.780499)
(xy 140.41772 95.721477)
(xy 140.327983 95.59147)
(xy 140.20974 95.486717)
(xy 140.209738 95.486716)
(xy 140.209737 95.486715)
(xy 140.069865 95.413303)
(xy 139.916486 95.3755)
(xy 139.916485 95.3755)
(xy 139.758515 95.3755)
(xy 139.758514 95.3755)
(xy 139.605134 95.413303)
(xy 139.465262 95.486715)
(xy 139.445213 95.504477)
(xy 139.350317 95.588547)
(xy 139.347016 95.591471)
(xy 139.257281 95.721475)
(xy 139.25728 95.721476)
(xy 139.201262 95.869181)
(xy 139.182222 96.025999)
(xy 139.182222 96.026)
(xy 137.7084 96.026)
(xy 137.7084 84.0715)
(xy 137.728085 84.004461)
(xy 137.780889 83.958706)
(xy 137.8324 83.9475)
(xy 157.0253 83.9475)
New branch for new revision
2024-03-12 11:46:53 +01:00
)
)
(filled_polygon
(layer "B.Cu")
(pts
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 157.092339 83.967185)
(xy 157.138094 84.019989)
(xy 157.1493 84.0715)
(xy 157.1493 108.1663)
(xy 157.129615 108.233339)
(xy 157.076811 108.279094)
(xy 157.0253 108.2903)
(xy 137.8324 108.2903)
(xy 137.765361 108.270615)
(xy 137.719606 108.217811)
(xy 137.7084 108.1663)
(xy 137.7084 101.487)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 139.182222 101.487)
(xy 139.201262 101.643818)
(xy 139.25728 101.791523)
(xy 139.347017 101.92153)
(xy 139.46526 102.026283)
(xy 139.465262 102.026284)
(xy 139.605134 102.099696)
(xy 139.758514 102.1375)
(xy 139.758515 102.1375)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 139.916484 102.1375)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 139.916485 102.1375)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 140.057002 102.102865)
(xy 140.063766 102.101496)
(xy 140.065187 102.101123)
(xy 140.065196 102.101123)
(xy 140.674044 101.94155)
(xy 140.705481 101.9375)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 153.394238 101.9375)
(xy 153.40812 101.938279)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 153.420921 101.939722)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 153.443533 101.94227)
(xy 153.443533 101.942269)
(xy 153.443535 101.94227)
(xy 153.499736 101.931635)
(xy 153.504226 101.930872)
(xy 153.560787 101.922348)
(xy 153.560791 101.922345)
(xy 153.568947 101.91983)
(xy 153.576969 101.917024)
(xy 153.57697 101.917023)
(xy 153.576972 101.917023)
(xy 153.627588 101.89027)
(xy 153.631593 101.888248)
(xy 153.683142 101.863425)
(xy 153.683143 101.863423)
(xy 153.683145 101.863423)
(xy 153.690195 101.858616)
(xy 153.697034 101.853567)
(xy 153.697038 101.853566)
(xy 153.737475 101.813127)
(xy 153.740761 101.809961)
(xy 153.782694 101.771055)
(xy 153.782696 101.77105)
(xy 153.788487 101.76379)
(xy 153.789143 101.764313)
(xy 153.798532 101.75207)
(xy 154.103249 101.447353)
(xy 154.113598 101.438105)
(xy 154.14147 101.415879)
(xy 154.173689 101.36862)
(xy 154.176302 101.364936)
(xy 154.210293 101.318883)
(xy 154.210295 101.318874)
(xy 154.214286 101.311324)
(xy 154.217968 101.303678)
(xy 154.217972 101.303673)
(xy 154.234827 101.249022)
(xy 154.236272 101.244635)
(xy 154.255146 101.1907)
(xy 154.255146 101.190696)
(xy 154.256727 101.182341)
(xy 154.258 101.173899)
(xy 154.258 101.116738)
(xy 154.258087 101.1121)
(xy 154.260224 101.054992)
(xy 154.259184 101.045761)
(xy 154.260013 101.045667)
(xy 154.258 101.030366)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 154.258 93.795409)
(xy 154.260715 93.769601)
(xy 154.276037 93.697596)
(xy 154.391636 93.154348)
(xy 154.391637 93.154327)
(xy 154.3917 93.15387)
(xy 154.391931 93.152959)
(xy 154.392604 93.149797)
(xy 154.392726 93.149823)
(xy 154.398639 93.126526)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 154.410437 93.095418)
(xy 154.429478 92.9386)
(xy 154.410437 92.781782)
(xy 154.35442 92.634077)
(xy 154.264683 92.50407)
(xy 154.14644 92.399317)
(xy 154.146438 92.399316)
(xy 154.146437 92.399315)
(xy 154.006565 92.325903)
(xy 153.853186 92.2881)
(xy 153.853185 92.2881)
(xy 153.695215 92.2881)
(xy 153.695214 92.2881)
(xy 153.541834 92.325903)
(xy 153.401962 92.399315)
(xy 153.283716 92.504071)
(xy 153.193981 92.634075)
(xy 153.19398 92.634076)
(xy 153.137962 92.781781)
(xy 153.118922 92.938599)
(xy 153.118922 92.9386)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 153.137962 93.095414)
(xy 153.137964 93.095423)
(xy 153.156524 93.144361)
(xy 153.163826 93.17466)
(xy 153.164311 93.179038)
(xy 153.164312 93.179043)
(xy 153.164313 93.179045)
(xy 153.347947 93.758687)
(xy 153.35121 93.768985)
(xy 153.357 93.806435)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 153.357 100.868035)
(xy 153.337315 100.935074)
(xy 153.320681 100.955716)
(xy 153.276216 101.000181)
(xy 153.214893 101.033666)
(xy 153.188535 101.0365)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 140.705482 101.0365)
(xy 140.674045 101.032449)
(xy 140.666097 101.030366)
(xy 140.588613 101.010058)
(xy 140.06518 100.872872)
(xy 140.057221 100.871187)
(xy 140.044432 100.868035)
(xy 140.037358 100.866291)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 139.916486 100.8365)
(xy 139.916485 100.8365)
(xy 139.758515 100.8365)
(xy 139.758514 100.8365)
(xy 139.605134 100.874303)
(xy 139.465262 100.947715)
(xy 139.46526 100.947717)
(xy 139.353543 101.046689)
(xy 139.347016 101.052471)
(xy 139.257281 101.182475)
(xy 139.25728 101.182476)
(xy 139.201262 101.330181)
(xy 139.182222 101.486999)
(xy 139.182222 101.487)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 137.7084 101.487)
(xy 137.7084 96.026)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 139.182222 96.026)
(xy 139.201262 96.182818)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 139.25728 96.330522)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 139.25728 96.330523)
(xy 139.347017 96.46053)
(xy 139.46526 96.565283)
(xy 139.465262 96.565284)
(xy 139.605134 96.638696)
(xy 139.758514 96.6765)
(xy 139.758515 96.6765)
(xy 139.916485 96.6765)
(xy 140.069865 96.638696)
(xy 140.20974 96.565283)
(xy 140.327983 96.46053)
(xy 140.41772 96.330523)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 140.430358 96.297197)
(xy 140.442977 96.27261)
(xy 140.447869 96.265239)
(xy 140.462548 96.229477)
(xy 140.568878 95.970416)
(xy 140.612543 95.915872)
(xy 140.678766 95.893594)
(xy 140.683591 95.8935)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 144.333974 95.8935)
(xy 144.401013 95.913185)
(xy 144.446768 95.965989)
(xy 144.456712 96.035147)
(xy 144.430424 96.092708)
(xy 144.431278 96.093297)
(xy 144.427961 96.098101)
(xy 144.427687 96.098703)
(xy 144.427027 96.099454)
(xy 144.337281 96.229475)
(xy 144.33728 96.229476)
(xy 144.281262 96.377181)
(xy 144.262222 96.533999)
(xy 144.262222 96.534)
(xy 144.281262 96.690818)
(xy 144.319718 96.792216)
(xy 144.33728 96.838523)
(xy 144.427017 96.96853)
(xy 144.54526 97.073283)
(xy 144.545262 97.073284)
(xy 144.685134 97.146696)
(xy 144.838514 97.1845)
(xy 144.838515 97.1845)
(xy 144.996485 97.1845)
(xy 145.149865 97.146696)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 145.149873 97.146691)
(xy 145.156887 97.144033)
(xy 145.156993 97.144313)
(xy 145.165852 97.140842)
(xy 145.165799 97.1407)
(xy 145.756213 96.917511)
(xy 145.800059 96.9095)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 151.622996 96.9095)
(xy 151.648441 96.912139)
(xy 151.651524 96.912785)
(xy 151.659068 96.914367)
(xy 151.690476 96.910451)
(xy 151.705814 96.9095)
(xy 151.705912 96.9095)
(xy 151.705914 96.9095)
(xy 151.726443 96.906073)
(xy 151.731473 96.905341)
(xy 151.783426 96.898866)
(xy 151.783428 96.898864)
(xy 151.790941 96.896628)
(xy 151.798406 96.894066)
(xy 151.798406 96.894065)
(xy 151.79841 96.894065)
(xy 151.844436 96.869157)
(xy 151.848993 96.866812)
(xy 151.863902 96.859522)
(xy 151.896011 96.843826)
(xy 151.896013 96.843823)
(xy 151.902394 96.839268)
(xy 151.90862 96.834421)
(xy 151.908626 96.834419)
(xy 151.944093 96.79589)
(xy 151.947595 96.79224)
(xy 152.324089 96.415746)
(xy 152.343946 96.399622)
(xy 152.353036 96.393684)
(xy 152.372471 96.368712)
(xy 152.382656 96.357181)
(xy 152.382656 96.35718)
(xy 152.382719 96.357118)
(xy 152.39483 96.340153)
(xy 152.397827 96.336134)
(xy 152.430009 96.294789)
(xy 152.430011 96.294781)
(xy 152.433747 96.287878)
(xy 152.437206 96.280803)
(xy 152.43721 96.280799)
(xy 152.452142 96.230641)
(xy 152.453686 96.225818)
(xy 152.4707 96.17626)
(xy 152.4707 96.176258)
(xy 152.470701 96.176256)
(xy 152.471991 96.168524)
(xy 152.472968 96.160686)
(xy 152.470806 96.108407)
(xy 152.4707 96.103283)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 152.4707 93.79576)
(xy 152.478711 93.751914)
(xy 152.536478 93.599099)
(xy 152.699745 93.167199)
(xy 152.702152 93.153459)
(xy 152.708347 93.1309)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 152.731437 93.070018)
(xy 152.750478 92.9132)
(xy 152.731437 92.756382)
(xy 152.67542 92.608677)
(xy 152.585683 92.47867)
(xy 152.46744 92.373917)
(xy 152.467438 92.373916)
(xy 152.467437 92.373915)
(xy 152.327565 92.300503)
(xy 152.174186 92.2627)
(xy 152.174185 92.2627)
(xy 152.016215 92.2627)
(xy 152.016214 92.2627)
(xy 151.862834 92.300503)
(xy 151.722962 92.373915)
(xy 151.604716 92.478671)
(xy 151.514981 92.608675)
(xy 151.51498 92.608676)
(xy 151.458962 92.756381)
(xy 151.439922 92.913199)
(xy 151.439922 92.9132)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 151.458962 93.070014)
(xy 151.458964 93.070023)
(xy 151.482252 93.131428)
(xy 151.488624 93.155017)
(xy 151.490654 93.1672)
(xy 151.692882 93.702165)
(xy 151.711689 93.751914)
(xy 151.7197 93.795761)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 151.7197 95.077167)
(xy 151.700015 95.144206)
(xy 151.647211 95.189961)
(xy 151.578053 95.199905)
(xy 151.566026 95.197564)
(xy 151.407533 95.1585)
(xy 151.407532 95.1585)
(xy 151.249562 95.1585)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 151.096182 95.196304)
(xy 151.096179 95.196305)
(xy 151.089169 95.198964)
(xy 151.089064 95.198688)
(xy 151.08019 95.202164)
(xy 151.080242 95.202301)
(xy 150.882142 95.277187)
(xy 150.514219 95.41627)
(xy 150.489831 95.425489)
(xy 150.445985 95.4335)
(xy 148.37007 95.4335)
(xy 148.326224 95.425489)
(xy 147.756249 95.210026)
(xy 147.756246 95.210025)
(xy 147.744066 95.205421)
(xy 147.741504 95.204453)
(xy 147.741503 95.204452)
(xy 147.736056 95.202394)
(xy 147.736091 95.202299)
(xy 147.726985 95.19871)
(xy 147.726889 95.198964)
(xy 147.719876 95.196304)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 147.566494 95.1585)
(xy 147.566493 95.1585)
(xy 147.408523 95.1585)
(xy 147.408522 95.1585)
(xy 147.255142 95.196303)
(xy 147.115269 95.269715)
(xy 147.110837 95.272775)
(xy 147.044481 95.294655)
(xy 146.97683 95.277187)
(xy 146.938351 95.241162)
(xy 146.880903 95.157935)
(xy 146.863409 95.13259)
(xy 146.745166 95.027837)
(xy 146.745164 95.027836)
(xy 146.745163 95.027835)
(xy 146.605291 94.954423)
(xy 146.451912 94.91662)
(xy 146.451911 94.91662)
(xy 146.293941 94.91662)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 146.14026 94.954498)
(xy 146.133751 94.956728)
(xy 145.545862 95.137049)
(xy 145.5095 95.1425)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 144.51064 95.1425)
(xy 144.443601 95.122815)
(xy 144.397846 95.070011)
(xy 144.387902 95.000853)
(xy 144.40859 94.94806)
(xy 144.422709 94.927605)
(xy 144.44582 94.894123)
(xy 144.501837 94.746418)
(xy 144.520878 94.5896)
(xy 144.501837 94.432782)
(xy 144.44582 94.285077)
(xy 144.356083 94.15507)
(xy 144.23784 94.050317)
(xy 144.237838 94.050316)
(xy 144.237837 94.050315)
(xy 144.097965 93.976903)
(xy 143.944586 93.9391)
(xy 143.944585 93.9391)
(xy 143.786615 93.9391)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 143.786612 93.9391)
(xy 143.646101 93.973731)
(xy 143.639294 93.975111)
(xy 143.029053 94.135049)
(xy 142.997616 94.1391)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 141.969966 94.1391)
(xy 141.902927 94.119415)
(xy 141.882285 94.102781)
(xy 141.253619 93.474115)
(xy 141.220134 93.412792)
(xy 141.2173 93.386434)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 141.2173 92.612781)
(xy 141.221351 92.581344)
(xy 141.241603 92.504071)
(xy 141.380923 91.972496)
(xy 141.380935 91.972371)
(xy 141.380978 91.972184)
(xy 141.381801 91.967547)
(xy 141.382046 91.96759)
(xy 141.38844 91.940107)
(xy 141.403036 91.90162)
(xy 141.403035 91.90162)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 141.403037 91.901618)
(xy 141.422078 91.7448)
(xy 141.403037 91.587982)
(xy 141.34702 91.440277)
(xy 141.257283 91.31027)
(xy 141.13904 91.205517)
(xy 141.139038 91.205516)
(xy 141.139037 91.205515)
(xy 140.999165 91.132103)
(xy 140.845786 91.0943)
(xy 140.845785 91.0943)
(xy 140.687815 91.0943)
(xy 140.687814 91.0943)
(xy 140.534434 91.132103)
(xy 140.394562 91.205515)
(xy 140.276316 91.310271)
(xy 140.186581 91.440275)
(xy 140.18658 91.440276)
(xy 140.130562 91.587981)
(xy 140.111522 91.744799)
(xy 140.111522 91.7448)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 140.130562 91.901616)
(xy 140.145077 91.939889)
(xy 140.150814 91.966619)
(xy 140.151716 91.966476)
(xy 140.152675 91.972491)
(xy 140.228736 92.2627)
(xy 140.291996 92.504071)
(xy 140.312249 92.581344)
(xy 140.3163 92.612781)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 140.3163 93.592138)
(xy 140.31552 93.606023)
(xy 140.311529 93.641436)
(xy 140.322155 93.697596)
(xy 140.322932 93.702165)
(xy 140.331452 93.758691)
(xy 140.333962 93.766827)
(xy 140.336776 93.77487)
(xy 140.363488 93.825411)
(xy 140.365576 93.829549)
(xy 140.390374 93.881041)
(xy 140.395162 93.888065)
(xy 140.400231 93.894932)
(xy 140.400234 93.894938)
(xy 140.400238 93.894942)
(xy 140.440646 93.93535)
(xy 140.443863 93.938689)
(xy 140.482747 93.980596)
(xy 140.49001 93.986388)
(xy 140.489489 93.987041)
(xy 140.50173 93.996434)
(xy 141.39063 94.885333)
(xy 141.399895 94.8957)
(xy 141.422122 94.923571)
(xy 141.426469 94.927605)
(xy 141.462221 94.987634)
(xy 141.459843 95.057463)
(xy 141.420091 95.114922)
(xy 141.355584 95.141767)
(xy 141.342124 95.1425)
(xy 140.397304 95.1425)
(xy 140.371857 95.139861)
(xy 140.361231 95.137633)
(xy 140.36123 95.137633)
(xy 140.329825 95.141548)
(xy 140.314486 95.1425)
(xy 140.314384 95.1425)
(xy 140.293867 95.145923)
(xy 140.288822 95.146658)
(xy 140.268696 95.149167)
(xy 140.236868 95.153135)
(xy 140.229344 95.155375)
(xy 140.221888 95.157935)
(xy 140.175857 95.182844)
(xy 140.171307 95.185186)
(xy 140.124291 95.208171)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 140.117895 95.212737)
(xy 140.111672 95.217582)
(xy 140.110329 95.219041)
(xy 140.106819 95.221359)
(xy 140.103567 95.223891)
(xy 140.10337 95.223638)
(xy 140.06056 95.251918)
(xy 139.612501 95.410862)
(xy 139.60806 95.412194)
(xy 139.601947 95.414513)
(xy 139.599053 95.415842)
(xy 139.597543 95.416634)
(xy 139.587895 95.422351)
(xy 139.46526 95.486717)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 139.347016 95.591471)
(xy 139.257281 95.721475)
(xy 139.25728 95.721476)
(xy 139.201262 95.869181)
(xy 139.182222 96.025999)
(xy 139.182222 96.026)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 137.7084 96.026)
(xy 137.7084 84.0715)
(xy 137.728085 84.004461)
(xy 137.780889 83.958706)
(xy 137.8324 83.9475)
(xy 157.0253 83.9475)
)
)
)
(zone (net 15) (net_name "SPI_CS") (layer "B.Cu") (tstamp 09968897-e2ac-47ec-92ee-02324e8e7c3f) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30006)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 148.287508 95.934)
(xy 148.287508 95.684)
(xy 147.640581 95.439448)
(xy 147.486508 95.809)
(xy 147.640581 96.178552)
)
)
(filled_polygon
(layer "B.Cu")
(pts
(xy 147.668204 95.44989)
(xy 148.279945 95.681141)
(xy 148.286472 95.687272)
(xy 148.287508 95.692085)
(xy 148.287508 95.925914)
(xy 148.284081 95.934187)
(xy 148.279945 95.936858)
(xy 147.651163 96.174551)
(xy 147.642213 96.174271)
(xy 147.636227 96.168109)
(xy 147.539814 95.936858)
(xy 147.488383 95.813499)
(xy 147.488363 95.80455)
(xy 147.636227 95.449889)
(xy 147.642574 95.443572)
(xy 147.651162 95.443448)
)
)
)
(zone (net 3) (net_name "SPI_CLK") (layer "B.Cu") (tstamp 0d3c2f49-fdbc-414d-9bd9-ce4ed52a1869) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30009)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 140.42708 95.643)
(xy 140.42708 95.393)
(xy 139.684427 95.656448)
(xy 139.8365 96.026)
(xy 140.207052 96.179073)
)
)
(filled_polygon
(layer "B.Cu")
(pts
(xy 140.420411 95.399002)
(xy 140.426407 95.405653)
(xy 140.42708 95.409565)
(xy 140.42708 95.640691)
(xy 140.426204 95.645134)
(xy 140.211504 96.168224)
(xy 140.205192 96.174576)
(xy 140.196237 96.174605)
(xy 140.196213 96.174595)
(xy 139.840999 96.027858)
(xy 139.834661 96.021532)
(xy 139.689105 95.667815)
(xy 139.689126 95.658862)
(xy 139.695473 95.652544)
(xy 139.695978 95.65235)
(xy 140.411468 95.398538)
)
)
)
(zone (net 15) (net_name "SPI_CS") (layer "B.Cu") (tstamp 313f43df-d6b3-4bff-93bf-488713699bf4) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30007)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 150.528547 95.684)
(xy 150.528547 95.934)
(xy 151.175474 96.178552)
(xy 151.329547 95.809)
(xy 151.175474 95.439448)
)
)
(filled_polygon
(layer "B.Cu")
(pts
(xy 151.173841 95.443728)
(xy 151.179827 95.44989)
(xy 151.32767 95.804498)
(xy 151.327691 95.813452)
(xy 151.32767 95.813502)
(xy 151.179827 96.168109)
(xy 151.17348 96.174427)
(xy 151.164891 96.174551)
(xy 150.53611 95.936858)
(xy 150.529583 95.930727)
(xy 150.528547 95.925914)
(xy 150.528547 95.692085)
(xy 150.531974 95.683812)
(xy 150.53611 95.681141)
(xy 151.164892 95.443448)
)
)
)
(zone (net 3) (net_name "SPI_CLK") (layer "B.Cu") (tstamp 5fc58ec8-5520-4991-9e42-80d66cef59d2) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30008)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 145.582697 95.393)
(xy 145.582697 95.643)
(xy 146.219853 95.936672)
(xy 146.373926 95.56712)
(xy 146.219853 95.197568)
)
)
(filled_polygon
(layer "B.Cu")
(pts
(xy 146.218621 95.20153)
(xy 146.223936 95.207362)
(xy 146.301332 95.393)
(xy 146.372049 95.562618)
(xy 146.37207 95.571572)
(xy 146.372049 95.571622)
(xy 146.224524 95.925466)
(xy 146.218177 95.931784)
(xy 146.209223 95.931763)
(xy 146.208828 95.93159)
(xy 145.5895 95.646135)
(xy 145.58342 95.639559)
(xy 145.582697 95.635509)
(xy 145.582697 95.401649)
(xy 145.586124 95.393376)
(xy 145.590963 95.390464)
(xy 146.209709 95.200679)
)
)
)
(zone (net 13) (net_name "VDD") (layer "B.Cu") (tstamp 788e5d57-e0a6-4288-a290-aa85a78fd2f9) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30001)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 140.6375 101.687)
(xy 140.6375 101.287)
(xy 139.990573 101.117448)
(xy 139.8365 101.487)
(xy 139.990573 101.856552)
)
)
(filled_polygon
(layer "B.Cu")
(pts
(xy 140.628767 101.284711)
(xy 140.6359 101.290123)
(xy 140.6375 101.296028)
(xy 140.6375 101.677971)
(xy 140.634073 101.686244)
(xy 140.628766 101.689289)
(xy 140.00042 101.853971)
(xy 139.991549 101.852753)
(xy 139.986655 101.847155)
(xy 139.838375 101.491499)
(xy 139.838355 101.48255)
(xy 139.986656 101.126842)
(xy 139.993002 101.120526)
(xy 140.000417 101.120028)
)
)
)
(zone (net 13) (net_name "VDD") (layer "B.Cu") (tstamp 7c186834-e92c-4bae-b4bf-935ac4c96f15) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30000)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 140.5668 92.5448)
(xy 140.9668 92.5448)
(xy 141.136352 91.897873)
(xy 140.7668 91.7438)
(xy 140.397248 91.897873)
)
)
(filled_polygon
(layer "B.Cu")
(pts
(xy 141.126955 91.893955)
(xy 141.133273 91.900302)
(xy 141.133771 91.90772)
(xy 140.969089 92.536066)
(xy 140.963676 92.5432)
(xy 140.957771 92.5448)
(xy 140.575829 92.5448)
(xy 140.567556 92.541373)
(xy 140.564511 92.536066)
(xy 140.549385 92.478353)
(xy 140.399828 91.907718)
(xy 140.401046 91.898849)
(xy 140.406642 91.893956)
(xy 140.7623 91.745675)
(xy 140.771249 91.745655)
)
)
)
(zone (net 13) (net_name "VDD") (layer "B.Cu") (tstamp 88a212b7-1f63-4ca4-a519-76cdf17f9d4c) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30003)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 153.6075 93.731976)
(xy 154.0075 93.731976)
(xy 154.143752 93.091673)
(xy 153.7742 92.9376)
(xy 153.404648 93.091673)
)
)
(filled_polygon
(layer "B.Cu")
(pts
(xy 154.133863 93.08755)
(xy 154.134789 93.087936)
(xy 154.141107 93.094283)
(xy 154.141731 93.10117)
(xy 154.009472 93.722711)
(xy 154.004398 93.73009)
(xy 153.998028 93.731976)
(xy 153.616067 93.731976)
(xy 153.607794 93.728549)
(xy 153.604913 93.72381)
(xy 153.59246 93.684502)
(xy 153.407882 93.101881)
(xy 153.408651 93.092961)
(xy 153.414531 93.087552)
(xy 153.7697 92.939475)
(xy 153.778649 92.939455)
)
)
)
(zone (net 5) (net_name "SPI_MISO") (layer "B.Cu") (tstamp e1441791-c250-492f-8b67-7ef4208c009f) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30005)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 151.9702 93.7132)
(xy 152.2202 93.7132)
(xy 152.464752 93.066273)
(xy 152.0952 92.9122)
(xy 151.725648 93.066273)
)
)
(filled_polygon
(layer "B.Cu")
(pts
(xy 152.454309 93.061919)
(xy 152.460627 93.068266)
(xy 152.460751 93.076855)
(xy 152.223059 93.705637)
(xy 152.216928 93.712164)
(xy 152.212115 93.7132)
(xy 151.978285 93.7132)
(xy 151.970012 93.709773)
(xy 151.967341 93.705637)
(xy 151.729648 93.076855)
(xy 151.729928 93.067905)
(xy 151.736089 93.061919)
(xy 152.0907 92.914075)
(xy 152.099649 92.914055)
)
)
)
(zone (net 5) (net_name "SPI_MISO") (layer "B.Cu") (tstamp f896693a-bc20-4ab2-9863-6cb66aad256e) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30004)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 145.7175 96.659)
(xy 145.7175 96.409)
(xy 145.070573 96.164448)
(xy 144.9165 96.534)
(xy 145.070573 96.903552)
)
)
(filled_polygon
(layer "B.Cu")
(pts
(xy 145.098196 96.17489)
(xy 145.709937 96.406141)
(xy 145.716464 96.412272)
(xy 145.7175 96.417085)
(xy 145.7175 96.650914)
(xy 145.714073 96.659187)
(xy 145.709937 96.661858)
(xy 145.081155 96.899551)
(xy 145.072205 96.899271)
(xy 145.066219 96.893109)
(xy 144.969806 96.661858)
(xy 144.918375 96.538499)
(xy 144.918355 96.52955)
(xy 145.066219 96.174889)
(xy 145.072566 96.168572)
(xy 145.081154 96.168448)
)
)
)
(zone (net 13) (net_name "VDD") (layer "B.Cu") (tstamp fd88156b-11c8-4b3b-ba19-0bce8cd47a66) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30002)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
(pts
(xy 143.0656 94.3896)
(xy 143.0656 94.7896)
(xy 143.712527 94.959152)
(xy 143.8666 94.5896)
(xy 143.712527 94.220048)
)
)
(filled_polygon
(layer "B.Cu")
(pts
(xy 143.71155 94.223846)
(xy 143.716444 94.229444)
(xy 143.864723 94.585098)
(xy 143.864744 94.594052)
(xy 143.864723 94.594102)
(xy 143.716444 94.949755)
(xy 143.710097 94.956073)
(xy 143.702679 94.956571)
(xy 143.074334 94.791889)
(xy 143.0672 94.786476)
(xy 143.0656 94.780571)
(xy 143.0656 94.398628)
(xy 143.069027 94.390355)
(xy 143.074331 94.387311)
(xy 143.702681 94.222628)
New branch for new revision
2024-03-12 11:46:53 +01:00
)
)
)
)