LoopAware/Replacement-TPM-2.0-module
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Replacement-TPM-2.0-module
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Replacement-TPM-2.0-module/tpm-module-14pin-spi-MZ32-A.../Revision A3/tpm-module-14pin-spi-RevA3/tpm-module-14pin-spi-RevA3....

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New branch for new revision
2024-03-12 11:46:53 +01:00
(kicad_pcb (version 20221018) (generator pcbnew)
(general
(thickness 1.6)
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(paper "A4")
(layers
(0 "F.Cu" signal)
(31 "B.Cu" signal)
(32 "B.Adhes" user "B.Adhesive")
(33 "F.Adhes" user "F.Adhesive")
(34 "B.Paste" user)
(35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen")
(37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user)
(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user)
(45 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard")
(47 "F.CrtYd" user "F.Courtyard")
(48 "B.Fab" user)
(49 "F.Fab" user)
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(55 "User.6" user)
(56 "User.7" user)
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(58 "User.9" user)
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(layer "F.Paste" (type "Top Solder Paste"))
(layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
(layer "F.Cu" (type "copper") (thickness 0.035))
(layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
(layer "B.Cu" (type "copper") (thickness 0.035))
(layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
(layer "B.Paste" (type "Bottom Solder Paste"))
(layer "B.SilkS" (type "Bottom Silk Screen"))
(layer "F.SilkS" (type "Top Silk Screen"))
(layer "F.Paste" (type "Top Solder Paste"))
(layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
(layer "F.Cu" (type "copper") (thickness 0.035))
(layer "dielectric 2" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
(layer "B.Cu" (type "copper") (thickness 0.035))
(layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
(layer "B.Paste" (type "Bottom Solder Paste"))
(layer "B.SilkS" (type "Bottom Silk Screen"))
(layer "F.SilkS" (type "Top Silk Screen"))
(layer "F.Paste" (type "Top Solder Paste"))
(layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
(layer "F.Cu" (type "copper") (thickness 0.035))
(layer "dielectric 3" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
(layer "B.Cu" (type "copper") (thickness 0.035))
(layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
(layer "B.Paste" (type "Bottom Solder Paste"))
(layer "B.SilkS" (type "Bottom Silk Screen"))
(copper_finish "None")
(dielectric_constraints no)
)
(pad_to_mask_clearance 0)
(pcbplotparams
(layerselection 0x00010fc_ffffffff)
(plot_on_all_layers_selection 0x0000000_00000000)
(disableapertmacros false)
(usegerberextensions false)
(usegerberattributes true)
(usegerberadvancedattributes true)
(creategerberjobfile true)
(dashed_line_dash_ratio 12.000000)
(dashed_line_gap_ratio 3.000000)
(svgprecision 6)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(dxfpolygonmode true)
(dxfimperialunits true)
(dxfusepcbnewfont true)
(psnegative false)
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(plotreference true)
(plotvalue true)
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(sketchpadsonfab false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory "")
)
)
(net 0 "")
(net 1 "GND")
(net 2 "IRQ")
(net 3 "SPI_CLK")
(net 4 "SPI_MOSI")
(net 5 "SPI_MISO")
(net 6 "unconnected-(IC1-GPIO-Pad6)")
(net 7 "unconnected-(IC1-PP-Pad7)")
(net 8 "unconnected-(J1-Pin_4-Pad4)")
(net 9 "unconnected-(J1-Pin_8-Pad8)")
(net 10 "unconnected-(J1-Pin_9-Pad9)")
(net 11 "unconnected-(J1-Pin_10-Pad10)")
(net 12 "unconnected-(J1-Pin_11-Pad11)")
(net 13 "VDD")
(net 14 "RESET")
(net 15 "SPI_CS")
(footprint "Capacitor_SMD:C_0402_1005Metric" (layer "F.Cu")
(tstamp 0d48f3de-429a-44f6-87e8-8f0675772236)
(at 145.796 86.8452 90)
(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
(tags "capacitor")
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(property "Sheetfile" "tpm-module-14pin-spi-RevA3.kicad_sch")
New branch for new revision
2024-03-12 11:46:53 +01:00
(property "Sheetname" "")
(property "ki_description" "Unpolarized capacitor")
(property "ki_keywords" "cap capacitor")
(path "/02bd4d54-882e-439e-b1c2-88f37e7d09b2")
(attr smd)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(fp_text reference "C2" (at -0.0228 -1.1176 270) (layer "F.SilkS")
New branch for new revision
2024-03-12 11:46:53 +01:00
(effects (font (size 1 1) (thickness 0.15)))
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(fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.Fab")
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(pad "1" smd roundrect (at -0.48 0 90) (size 0.56 0.62) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 13 "VDD") (pintype "passive") (tstamp c1c6a7a9-b34f-4251-a2c4-95c09eb7c2fb))
(pad "2" smd roundrect (at 0.48 0 90) (size 0.56 0.62) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 1 "GND") (pintype "passive") (zone_connect 2) (tstamp 4647e9a0-baf1-4e6c-a1e1-8365d460a298))
(model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(footprint "Resistor_SMD:R_0402_1005Metric" (layer "F.Cu")
(tstamp 1769a4ee-56a4-4b21-a55b-38833d8b6900)
(at 144.7292 95.504)
(descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
(tags "resistor")
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(property "Sheetfile" "tpm-module-14pin-spi-RevA3.kicad_sch")
New branch for new revision
2024-03-12 11:46:53 +01:00
(property "Sheetname" "")
(property "ki_description" "Resistor")
(property "ki_keywords" "R res resistor")
(path "/c7fefcf9-ba90-436b-87c6-c31455c0a6e5")
(attr smd)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(fp_text reference "R2" (at -0.762 -1.0668) (layer "F.SilkS")
New branch for new revision
2024-03-12 11:46:53 +01:00
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(pad "1" smd roundrect (at -0.51 0) (size 0.54 0.64) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 13 "VDD") (pintype "passive") (tstamp 5642456e-136d-4324-94f6-e5084e15f21c))
(pad "2" smd roundrect (at 0.51 0) (size 0.54 0.64) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 2 "IRQ") (pintype "passive") (tstamp e2474ed4-956e-41fd-b29a-7fddc05c1123))
(model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(footprint "Connector_PinSocket_2.00mm:PinSocket_2x07_P2.00mm_Vertical_SMD" (layer "F.Cu")
New branch for new revision
2024-03-12 11:46:53 +01:00
(tstamp 53a533d2-704b-49aa-a740-67c21ceb6b4f)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(at 147.4575 101.931 90)
(descr "surface-mounted straight socket strip, 2x07, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated")
(tags "Surface mounted socket strip SMD 2x07 2.00mm double row")
(property "Sheetfile" "tpm-module-14pin-spi-RevA3.kicad_sch")
New branch for new revision
2024-03-12 11:46:53 +01:00
(property "Sheetname" "")
(property "ki_description" "Generic connector, double row, 02x07, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/)")
(property "ki_keywords" "connector")
(path "/7f7e32e8-e47e-41c2-adc4-ebdfb13f57e0")
(attr smd)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(fp_text reference "J1" (at 0 -8.5 90) (layer "F.SilkS")
New branch for new revision
2024-03-12 11:46:53 +01:00
(effects (font (size 1 1) (thickness 0.15)))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(tstamp e9cbc6c0-c345-4dd1-a977-319f16f2738c)
New branch for new revision
2024-03-12 11:46:53 +01:00
)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
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New branch for new revision
2024-03-12 11:46:53 +01:00
(effects (font (size 1 1) (thickness 0.15)))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
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New branch for new revision
2024-03-12 11:46:53 +01:00
)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(fp_text user "${REFERENCE}" (at 0 0 180) (layer "F.Fab")
New branch for new revision
2024-03-12 11:46:53 +01:00
(effects (font (size 1 1) (thickness 0.15)))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
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New branch for new revision
2024-03-12 11:46:53 +01:00
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
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New branch for new revision
2024-03-12 11:46:53 +01:00
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
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New branch for new revision
2024-03-12 11:46:53 +01:00
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
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New branch for new revision
2024-03-12 11:46:53 +01:00
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
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2024-03-12 14:01:42 +01:00
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
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(pad "25" smd roundrect (at 1.75 -2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp e1b27ea4-deed-4a95-8fd5-4aa705eee923))
(pad "26" smd roundrect (at 1.25 -2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 9815e798-e94a-4c6b-b2b2-4947553ac2fc))
(pad "27" smd roundrect (at 0.75 -2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 6ea7b7d6-e1f7-4a69-9266-2084348add3a))
(pad "28" smd roundrect (at 0.25 -2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 275d2652-9109-43a6-94b4-5441eb95638a))
(pad "29" smd roundrect (at -0.25 -2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp e6a8ee3b-abe6-4413-8ede-ba854d88be35))
(pad "30" smd roundrect (at -0.75 -2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 72e30e39-0985-4568-98d3-bf106378704e))
(pad "31" smd roundrect (at -1.25 -2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 1006d333-5c0b-497a-974b-fd14bfdc4fe5))
(pad "32" smd roundrect (at -1.75 -2.4375 270) (size 0.25 0.875) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 1 "GND") (pinfunction "GND") (pintype "power_in") (zone_connect 2) (tstamp 711aab4b-918b-47b8-8ad7-c24e42ad0e4e))
(pad "33" smd rect (at 0 0 270) (size 3.1 3.1) (property pad_prop_heatsink) (layers "F.Cu" "F.Mask")
(net 1 "GND") (pinfunction "GND") (pintype "power_in") (zone_connect 2) (tstamp af1e8727-c081-4420-82fa-1a97cfa5a763))
(model "${KICAD7_3DMODEL_DIR}/Package_DFN_QFN.3dshapes/QFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm.wrl"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
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(at 155.0924 95.25 -90)
(descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
(tags "resistor")
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(property "Sheetfile" "tpm-module-14pin-spi-RevA3.kicad_sch")
New branch for new revision
2024-03-12 11:46:53 +01:00
(property "Sheetname" "")
(property "ki_description" "Resistor")
(property "ki_keywords" "R res resistor")
(path "/65fbf09a-dd01-444a-b7c8-40da949ce9b7")
(attr smd)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(fp_text reference "R1" (at -0.0508 1.1176 90) (layer "F.SilkS")
New branch for new revision
2024-03-12 11:46:53 +01:00
(effects (font (size 1 1) (thickness 0.15)))
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(fp_text value "10k" (at 0 1.17 90) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
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(fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.Fab")
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(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp b6dc6901-56c6-4dee-92ba-ed339f181028))
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(pad "1" smd roundrect (at -0.51 0 270) (size 0.54 0.64) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 13 "VDD") (pintype "passive") (tstamp 5f5316ee-4ffe-4854-a51c-ee40f2cddf77))
(pad "2" smd roundrect (at 0.51 0 270) (size 0.54 0.64) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 15 "SPI_CS") (pintype "passive") (tstamp a95727f7-37a1-4ce6-988a-e44b32f4c9a6))
(model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
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(gr_rect (start 141.638 87.8332) (end 150.495 93.7438)
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(stroke (width 0.2) (type solid)) (fill solid) (layer "B.Mask") (tstamp e555e336-8e40-407b-ad0b-631d8e22573c))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(gr_rect (start 137.7079 83.947) (end 157.1498 108.2908)
New branch for new revision
2024-03-12 11:46:53 +01:00
(stroke (width 0.1) (type default)) (fill none) (layer "Edge.Cuts") (tstamp 03f55458-31de-47f0-adf3-0debc0a12b39))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(gr_text "LA-CTM010-R Rev.A3" (at 155.702 87.122) (layer "B.SilkS") (tstamp 8f9abfdb-79cc-4628-ac90-a4ddd8c3aa58)
New branch for new revision
2024-03-12 11:46:53 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify left bottom mirror))
)
(gr_text "LoopAware CTM010 \nReplacement Module" (at 147.193 105.41) (layer "B.SilkS") (tstamp de7ed673-bda4-4245-b857-e70c9c733eec)
(effects (font (size 1 1) (thickness 0.15)) (justify bottom mirror))
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(gr_text "LA-CTM010-R" (at 147.2184 86.614) (layer "F.SilkS") (tstamp edd14152-2dbf-43fc-ae5f-238f8ac1f4e3)
(effects (font (size 0.8 0.8) (thickness 0.15)) (justify left bottom))
New branch for new revision
2024-03-12 11:46:53 +01:00
)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(gr_text "LoopAware" (at 140.0556 95.1484 90) (layer "F.SilkS") (tstamp f06f8343-a7a0-4479-97db-9af7a1b1fd13)
New branch for new revision
2024-03-12 11:46:53 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify left bottom))
)
(gr_text "UNTESTED - COMES WITH NO WARRANTIES OR PROMISES\nTHIS MIGHT KILL YOUR COMPUTER AND SET YOUR HOUSE\nON FIRE, YOU HAVE BEEN WARNED." (at 147.0765 75.96) (layer "Dwgs.User") (tstamp a6bc2dbc-777b-4f4f-9a5f-6b04f6bdbd30)
(effects (font (size 1 1) (thickness 0.15)))
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 139.4714 105.537) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 08df0e97-cd68-4df3-a7c6-273707763312))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 147.574 91.2876) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 1) (tstamp 0ffef92d-0407-4f46-a2df-ecec26afd62d))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 156.5656 95.1992) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 10b50777-5c27-4edc-b101-e9a4df55f5c1))
(via (at 156.5656 96.3422) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 10e011ad-c390-4dfd-a982-05eb0395d9bf))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 149.733 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 1b0b17df-6dab-4008-a9fe-9333e5945266))
(via (at 148.59 92.3036) (size 1) (drill 0.4) (layers "F.Cu" "B.Cu") (net 1) (tstamp 1d4771a4-8821-4944-b979-33268f1dcdfd))
(via (at 144.018 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 1ddb4550-8046-44e1-89d1-726bd4f94400))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 138.2776 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 1de4b21e-7327-43b9-a844-1ceeab406131))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 152.6032 91.3892) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 2099cf62-9d6a-492c-873c-6e54824d1c8a))
(via (at 142.1384 88.5444) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 22036eb2-2a20-42bc-83bc-e34315eed58f))
(via (at 138.303 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 24dbf298-4aaf-4c85-9c19-f009d1b47597))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 153.162 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 24fce741-520b-45b1-84bf-316729053768))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 146.558 92.3036) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 1) (tstamp 2620b94a-bcd2-45fc-8fc7-e6b9ce8fdeb4))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 138.3284 91.821) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 2697c5c7-09a3-4ded-a329-b117d959cfcd))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 140.589 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 2c4d894b-ecc9-4cc8-b3ab-fb59b773056f))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 156.5656 105.4862) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 2f6d3d59-6b3c-4273-9131-c60ff341b690))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 146.558 90.2716) (size 1) (drill 0.4) (layers "F.Cu" "B.Cu") (net 1) (tstamp 2f9daf2e-333d-4116-9476-1ddff01e7b48))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 138.3284 92.964) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 33e21c97-a91b-4aa7-828d-99fd8645ac59))
(via (at 138.3284 99.822) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 35b67169-cddb-4ec7-a366-ec67074add52))
(via (at 138.3284 96.393) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 38bc7fef-431c-477a-9d90-faab293d0448))
(via (at 155.3972 104.3432) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 3992befb-f4ec-40f6-87cc-55002855c080))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 139.446 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 3db1dae6-1a22-41a7-9238-7f2f2d98b31d))
(via (at 145.161 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 3fd4b5a7-6812-4576-8d0d-951f9d904a3b))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 156.5656 92.9132) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 40e01510-490e-4629-91d3-a1110c9a6212))
(via (at 156.5656 103.2002) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 4100b76d-5405-4ad1-b177-92c89aa67f37))
(via (at 156.5656 88.3412) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 41140946-33dc-4efb-8126-b121771f954c))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 142.875 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 421f3aaf-a0b2-4f88-9d26-daed16159dab))
(via (at 141.732 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 433f90f4-c6ce-431c-82d0-177d5bddbc7f))
(via (at 148.59 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 436b5fce-da1b-4ce2-8d0e-2032d6a966e0))
(via (at 143.6624 92.9132) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 479df61c-87f3-4d2b-b3fe-6668a2c561c0))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 156.5656 91.7702) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 4b96baf5-5e8f-44f0-a410-788e33762322))
(via (at 138.3284 86.106) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 4e20cf14-c6de-4446-b689-4ec17f646cbc))
(via (at 145.161 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 5126d4ca-324c-4014-a351-b67f88699ae0))
(via (at 156.5656 89.4842) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 5164a61d-8dd8-4d27-932f-23d0af70272b))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 154.305 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 51aa3dc3-eef8-4410-9230-d4fdcc62d2b9))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 156.5656 100.9142) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 546a3685-ac10-42d8-922a-85f60944f9ea))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 156.591 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 563c1316-23ca-4899-8d6a-7e6874c35234))
(via (at 142.0876 90.424) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 57f57e30-5441-4ce7-824f-801e0592b85e))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 138.3284 105.537) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 5ec8cf1d-3ed9-412d-a279-9160252fdc57))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 146.304 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 608ba7dc-e7f5-4cd9-a9bc-cb9084f59d53))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 152.019 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 6358702f-ff1c-49ba-90c5-044a8b46600b))
(via (at 138.3284 97.536) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 636ab354-86ba-4033-93ac-ff3a31ddd433))
(via (at 156.5656 99.7712) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 6787631a-6cb2-4f20-b859-3c78fb672407))
(via (at 154.305 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 6dead5f2-5d5f-4578-881d-8ea17d91c296))
(via (at 155.3972 105.4862) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 6eb1dd7c-0c75-4d83-98ef-f9dead753e2b))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 143.7132 90.424) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 76630413-5b8d-4ba0-94d7-b54f6b19201d))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 140.589 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 7678049f-ebc7-4a03-a9f1-dcbf8a444262))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 151.2824 88.646) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 79f89881-2dbc-4cfa-a8ae-6e8be097867f))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 138.3284 98.679) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 807174f7-5b4a-4a28-9bfb-1fa309b33a49))
(via (at 138.3284 87.249) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 821e0569-a3cb-43b6-a970-4112f335a855))
(via (at 156.5656 104.3432) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 82b11adb-bf60-4458-86a9-39bb591460a4))
(via (at 156.5656 98.6282) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 841d8a5b-2e4a-4338-8727-d3b066493a3c))
(via (at 139.446 106.68) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 84cc33a1-e390-4996-86b3-5c032ff5a944))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 145.1864 94.5388) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 85482d54-83bb-4082-a6f6-df53d52dacec))
(via (at 152.019 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 892eb29f-590f-4bc6-b416-3c24c272f4ff))
(via (at 152.8572 95.1992) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 8c3ae359-764d-4b6c-94c1-1bd533fb6217))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 138.3284 89.535) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 8e608d58-7b86-4299-9430-14795bca7ea6))
(via (at 138.3284 102.108) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 91b7482e-a7fd-4236-adb2-5b7577634196))
(via (at 155.448 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 921f3552-10de-44bd-91c7-d81fd302aa82))
(via (at 156.5656 90.6272) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 9350a4ec-8e1a-4108-9dc0-c79b8b764706))
(via (at 147.447 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 9a38378f-213f-4335-8bbf-506692ad977c))
(via (at 139.446 98.679) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp 9d031a16-e2e7-46f8-8919-d2bd2ed9cfed))
(via (at 148.59 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp a13e5d23-a305-4e03-9f42-dea2fa9e99c6))
(via (at 146.304 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp a3b2019b-b5fb-4923-8ff0-4bee71f406bf))
(via (at 155.3972 99.7712) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp a6a5f8dc-d787-4e1b-978b-cb4e864f3f01))
(via (at 142.875 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp a7d743a7-1f2a-416e-872a-b94d2fda6e30))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 153.162 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp a8701b18-e9a1-4716-96b1-8b813a4fc765))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 138.3284 88.392) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp ab9081c5-5d8d-4286-b593-3267563ecc5c))
(via (at 156.5656 102.0572) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp ac7ff8c2-db97-4afa-9e88-9d0a1038d51d))
(via (at 156.5656 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp b21246ad-3e1d-4893-b943-4fb7ba8f0218))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 148.59 90.2716) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 1) (tstamp b6b46ec9-b709-46ae-b21f-a249a40c0181))
(via (at 147.447 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp b6e6a536-a38d-4172-a56b-2f3adc5f6937))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 138.3284 103.251) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp ba1078f0-745d-4b31-baad-6dd2f5411789))
(via (at 156.5656 94.0562) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp ba85a622-af12-458f-acc0-6c17c8f22e46))
(via (at 139.446 99.822) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp bd1ff15d-ddb7-4048-8aad-a89981153e9b))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 150.876 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp c047dd05-d0ca-4ea7-8051-f520a2f156bd))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 155.3972 103.2002) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp c0e9d8b8-7747-4b8a-8da7-5c927f961956))
(via (at 144.018 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp c302b13d-adca-4fa4-9542-55f35e8b3e96))
(via (at 155.3972 102.0572) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp c51e199e-cea4-4a7d-8deb-37d0eec02814))
(via (at 141.732 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp c54b1d92-dffe-449d-b9a3-eb0e272d0a14))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 152.6032 88.646) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp cc0ad23f-d2e8-47c7-93b0-0c993734dfaa))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 139.446 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp cef28706-8fef-46d8-b528-501a293bc95c))
(via (at 156.5656 87.1982) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp d186da34-3d84-4604-a8ba-d220ba9bc735))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 155.448 84.963) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp d4a1cf22-4d39-475a-84a8-52ab367bdc4e))
(via (at 138.303 106.68) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp d60ce66f-e47e-4390-900e-3fc0bfe64489))
(via (at 151.2824 91.3892) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp dbc9d70b-a0bf-4fa3-8b28-af5f4e3d20ea))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 150.876 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp dc7369c4-5e24-46e2-b7db-d18f5c75e10e))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 156.591 106.68) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp dd5c1d6e-692a-4b37-ad6d-b9c488d8bf13))
(via (at 143.7132 88.5444) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp e896de63-c80a-4345-a348-b4c0fe9a44e9))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(via (at 149.733 107.696) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp ea0cd1a3-e275-4e07-8287-c565720f712c))
(via (at 138.3284 95.25) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp ece93924-7f53-4c7c-998b-b85e26b1da10))
(via (at 156.5656 97.4852) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp ed65f487-2210-45ca-ac3b-5bf8a71cbf49))
(via (at 155.3972 100.9142) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp eda6c925-e834-45bb-a27b-f3344cf4c505))
(via (at 155.3972 98.6282) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp eea66e52-b337-4ee8-820b-45ea2eca5cbc))
(via (at 143.2052 96.3168) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp f0cc3d66-5467-4ec6-90e9-6fadb40d7fe8))
(via (at 138.3284 104.394) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp f0d73bc4-def7-47df-a0f3-4aae30ab3b35))
(via (at 138.3284 90.678) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp f1ac3dd0-5aa3-4d3a-a49f-6a4c7f7251c9))
(via (at 138.3284 94.107) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp f6417ba5-2f09-45ac-8b0a-99fada60124a))
(via (at 155.4226 106.68) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp f9e5c473-4770-416c-b16f-9aea24b82bbd))
(via (at 138.3284 100.965) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp fc79c446-11e4-4552-9a2c-6ca79d7b03df))
(via (at 156.5656 86.0552) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 1) (tstamp fcde5520-e403-4c09-9fa9-7a0a814f730b))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 145.2392 95.504) (end 145.647926 95.504) (width 0.25) (layer "F.Cu") (net 2) (tstamp 2e59c076-8de9-4aec-8233-33d06385b37f))
(segment (start 146.31 94.1175) (end 146.31 94.60474) (width 0.25) (layer "F.Cu") (net 2) (tstamp 34d4efda-f958-4c98-9511-f33cedc9e3c0))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 145.4575 104.612) (end 145.4575 101.9385) (width 0.25) (layer "F.Cu") (net 2) (tstamp 58670307-35c2-4bc7-a7ef-1506700034ae))
(segment (start 145.4575 101.9385) (end 146.4564 100.9396) (width 0.25) (layer "F.Cu") (net 2) (tstamp 7de98759-86c4-45b6-9ecc-9d55c633fb7d))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 145.647926 95.266815) (end 145.647926 95.504) (width 0.25) (layer "F.Cu") (net 2) (tstamp 96bb05fe-917b-4337-a0c2-1453733910aa))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 146.4564 100.9396) (end 146.4564 96.675899) (width 0.25) (layer "F.Cu") (net 2) (tstamp a3f72484-1442-44e9-b484-c5830eabb1d1))
(segment (start 146.4564 96.675899) (end 145.647926 95.867426) (width 0.25) (layer "F.Cu") (net 2) (tstamp ba45f0fd-1b5c-4a6d-b258-d8a5a1aa087b))
(segment (start 145.647926 95.867426) (end 145.647926 95.504) (width 0.25) (layer "F.Cu") (net 2) (tstamp d52fdf2a-6097-4e5e-af49-2758cab03a9e))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 146.31 94.60474) (end 145.647926 95.266815) (width 0.25) (layer "F.Cu") (net 2) (tstamp dd6710eb-1cd9-4469-8124-11bf75f5735d))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 140.5768 98.362) (end 139.8375 97.6227) (width 0.25) (layer "F.Cu") (net 3) (tstamp 064c1b4b-b13a-4a8d-909f-0b89e92a4e90))
(segment (start 141.4575 98.362) (end 140.5768 98.362) (width 0.25) (layer "F.Cu") (net 3) (tstamp 32dceb8b-a475-49d4-909b-5ea16efd058a))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 146.81 95.130046) (end 146.81 94.1175) (width 0.25) (layer "F.Cu") (net 3) (tstamp 64da7667-3087-4f67-8095-c4f9eaf1ef1f))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 139.8375 97.6227) (end 139.8375 96.026) (width 0.25) (layer "F.Cu") (net 3) (tstamp c44211ef-8a2a-4aa7-b28c-40c4ee7b240e))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 146.372926 95.56712) (end 146.81 95.130046) (width 0.25) (layer "F.Cu") (net 3) (tstamp e9628d51-10bd-4b05-9da9-196726a039b8))
(via (at 146.372926 95.56712) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 3) (tstamp 3e32fdcd-f6f0-4a66-bb57-eb7ecd62ccd9))
(via (at 139.8375 96.026) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 3) (tstamp b3a9e520-5b93-4fd8-ad10-d1e73233305b))
(segment (start 146.372926 95.56712) (end 146.323806 95.518) (width 0.25) (layer "B.Cu") (net 3) (tstamp a28037ad-7b98-4180-8d89-887741645a1f))
(segment (start 140.3455 95.518) (end 139.8375 96.026) (width 0.25) (layer "B.Cu") (net 3) (tstamp a7852601-ec93-4cf1-a24d-255f2f7ac69f))
(segment (start 146.323806 95.518) (end 140.3455 95.518) (width 0.25) (layer "B.Cu") (net 3) (tstamp d502eabc-0b08-44fd-9521-8211c8e19ac1))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 147.8788 101.346) (end 147.4575 100.9247) (width 0.25) (layer "F.Cu") (net 4) (tstamp 05d5c8d6-a8a0-4764-b5e7-eb9bc7590534))
(segment (start 148.082 101.346) (end 147.8788 101.346) (width 0.25) (layer "F.Cu") (net 4) (tstamp 40a1eae1-2c35-44e1-a9c5-0656dd10556d))
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(segment (start 148.4376 95.733787) (end 148.4376 100.9904) (width 0.25) (layer "F.Cu") (net 4) (tstamp d210ca0d-e361-4cd3-875b-1b42bb8bd76f))
(segment (start 147.81 94.1175) (end 147.81 95.106187) (width 0.25) (layer "F.Cu") (net 4) (tstamp d4c6f222-c919-4961-9918-f0c8c15d4cb3))
(segment (start 148.4376 100.9904) (end 148.082 101.346) (width 0.25) (layer "F.Cu") (net 4) (tstamp e5716ada-37cd-4fc3-b496-971b0899b8dc))
(segment (start 147.4575 98.806) (end 147.4575 100.9247) (width 0.25) (layer "F.Cu") (net 4) (tstamp feee654c-613a-4d6a-a447-b9a25e26ad25))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 149.31 93.7505) (end 150.8007 93.7505) (width 0.25) (layer "F.Cu") (net 5) (tstamp 1294bea3-ba1f-4f81-ac68-a993d641b522))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 145.4575 98.362) (end 145.4575 97.074) (width 0.25) (layer "F.Cu") (net 5) (tstamp 5608c48d-f1bb-486a-9e44-aa2aafe81bcb))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 150.8007 93.7505) (end 151.638 92.9132) (width 0.25) (layer "F.Cu") (net 5) (tstamp 6603b8b8-9880-428f-9b2b-a63b97008354))
(segment (start 151.638 92.9132) (end 152.0952 92.9132) (width 0.25) (layer "F.Cu") (net 5) (tstamp d2a543ef-7523-4b76-92b6-2d246b7d39dd))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 145.4575 97.074) (end 144.9175 96.534) (width 0.25) (layer "F.Cu") (net 5) (tstamp ddf3f96c-decc-42d9-b5a4-e265ff2d472b))
New branch for new revision
2024-03-12 11:46:53 +01:00
(via (at 152.0952 92.9132) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 5) (tstamp 36193547-ceee-4e72-b6bd-984be421024d))
(via (at 144.9175 96.534) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 5) (tstamp c6e20a54-f06c-4e8f-ad7a-28a1b7ff31ac))
(segment (start 152.0952 96.1136) (end 151.6748 96.534) (width 0.25) (layer "B.Cu") (net 5) (tstamp 0e964c7b-2386-46a6-9288-e6e64330c774))
(segment (start 152.0952 92.9132) (end 152.0952 96.1136) (width 0.25) (layer "B.Cu") (net 5) (tstamp adc44460-edb0-4e24-a7be-c59b5210d502))
(segment (start 151.6748 96.534) (end 144.9175 96.534) (width 0.25) (layer "B.Cu") (net 5) (tstamp f75918fa-4d44-4d44-a4e6-681f48705bf1))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 141.4575 104.612) (end 140.6292 104.612) (width 0.4) (layer "F.Cu") (net 13) (tstamp 0903ccfc-96a4-43f2-a205-39a4a3861e4b))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 155.0924 94.1324) (end 155.0924 92.3518) (width 0.4) (layer "F.Cu") (net 13) (tstamp 19d8ec36-9dee-4f68-a8bf-4d2f13102da1))
(segment (start 140.7668 91.7448) (end 140.7668 88.5444) (width 0.4) (layer "F.Cu") (net 13) (tstamp 1acc58f6-5e78-47a4-ae1c-b2f7fda59d58))
(segment (start 139.8515 101.473) (end 139.8375 101.487) (width 0.25) (layer "F.Cu") (net 13) (tstamp 1da3d8d2-53d9-4a96-93e2-cd937fcef469))
(segment (start 142.3924 91.7448) (end 143.51 91.7448) (width 0.4) (layer "F.Cu") (net 13) (tstamp 1fbee52a-cd7f-472e-a64e-8b35b9ee2ab9))
(segment (start 154.3792 94.74) (end 155.0924 94.74) (width 0.3) (layer "F.Cu") (net 13) (tstamp 24aaccab-ddae-4635-aa00-31bd1372238e))
(segment (start 150.876 94.6912) (end 151.4856 94.6912) (width 0.3) (layer "F.Cu") (net 13) (tstamp 2a98603d-56ef-494f-b839-1fe5c06698cf))
(segment (start 139.8235 101.473) (end 139.8375 101.487) (width 0.25) (layer "F.Cu") (net 13) (tstamp 2c328e89-79d8-4628-a825-103b62d10936))
(segment (start 153.7488 91.0336) (end 153.7488 88.2676) (width 0.4) (layer "F.Cu") (net 13) (tstamp 39c98f59-b96a-4a10-b7ee-f4d4f2c95d68))
(segment (start 149.9108 95.25) (end 150.3172 95.25) (width 0.3) (layer "F.Cu") (net 13) (tstamp 3e13326d-9b07-4b7e-bffd-86256b15f18d))
(segment (start 145.81 88.8755) (end 145.81 87.39) (width 0.3) (layer "F.Cu") (net 13) (tstamp 4083fb30-947c-4478-8b51-b3b925e2c88d))
(segment (start 140.7668 91.7448) (end 142.3924 91.7448) (width 0.4) (layer "F.Cu") (net 13) (tstamp 47975418-336a-4d56-a75f-3cc57b6f092b))
(segment (start 145.796 87.3252) (end 149.3012 87.3252) (width 0.4) (layer "F.Cu") (net 13) (tstamp 4ef7dd4d-7799-49cc-85b7-d35d2ffe6ec4))
(segment (start 154.0256 94.3864) (end 154.3792 94.74) (width 0.3) (layer "F.Cu") (net 13) (tstamp 54dd122c-6118-44c8-b955-713dbfcbe435))
(segment (start 141.986 87.3252) (end 145.796 87.3252) (width 0.4) (layer "F.Cu") (net 13) (tstamp 56cc296e-3712-4128-b032-2a516017e038))
(segment (start 142.3924 92.708) (end 142.3924 91.7448) (width 0.4) (layer "F.Cu") (net 13) (tstamp 5cd8e5a2-28bb-4950-8c04-164e5333cf33))
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(segment (start 140.7668 88.5444) (end 141.986 87.3252) (width 0.4) (layer "F.Cu") (net 13) (tstamp 6c420ed1-c024-43b9-a5eb-d9d8cdf19b04))
(segment (start 148.31 94.23774) (end 149.32226 95.25) (width 0.25) (layer "F.Cu") (net 13) (tstamp 72a54659-34e7-4d4b-a2da-dd6299d493e1))
(segment (start 143.8282 92.063) (end 145.1225 92.063) (width 0.25) (layer "F.Cu") (net 13) (tstamp 73109d04-b07c-4ae8-bf58-5b53a8b4eaaf))
(segment (start 143.8656 94.5896) (end 143.8656 95.1504) (width 0.25) (layer "F.Cu") (net 13) (tstamp 7b2d34cb-113b-445e-9d90-734974502711))
(segment (start 151.4856 94.6912) (end 151.7904 94.3864) (width 0.3) (layer "F.Cu") (net 13) (tstamp 7ebc9264-e61e-48b0-9928-8b5317e11d6b))
(segment (start 155.0924 94.74) (end 155.0924 94.1324) (width 0.4) (layer "F.Cu") (net 13) (tstamp 86c437bd-1e79-49fd-8619-a029fea31940))
(segment (start 149.3012 87.3252) (end 152.8064 87.3252) (width 0.4) (layer "F.Cu") (net 13) (tstamp 8e1d6dfb-779c-4cd0-b644-2e9bd7b95a59))
(segment (start 153.7742 92.0242) (end 153.7742 91.059) (width 0.4) (layer "F.Cu") (net 13) (tstamp a51d5fcc-caae-4712-8895-1e3e36107297))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 140.6292 104.612) (end 139.8375 103.8203) (width 0.4) (layer "F.Cu") (net 13) (tstamp ab514c3b-9e4c-4eba-8273-7271cf8ebbdb))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 149.32226 95.25) (end 149.9108 95.25) (width 0.25) (layer "F.Cu") (net 13) (tstamp b2bbb83b-cfd3-4376-90bb-56ad9cf3e1f8))
(segment (start 143.51 91.7448) (end 143.8282 92.063) (width 0.25) (layer "F.Cu") (net 13) (tstamp bd7ef63e-394a-4f91-95cc-f6c2d3a35d90))
(segment (start 149.31 88.8755) (end 149.31 87.334) (width 0.25) (layer "F.Cu") (net 13) (tstamp be38f4e8-ef61-429f-a714-0e727a9b53e1))
(segment (start 152.8064 87.3252) (end 153.7488 88.2676) (width 0.4) (layer "F.Cu") (net 13) (tstamp c07e72f9-54ca-49e2-bacf-9073b6bac702))
(segment (start 148.31 93.7505) (end 148.31 94.23774) (width 0.25) (layer "F.Cu") (net 13) (tstamp c07f5f52-cd13-4d62-9b56-93089fb67ed5))
(segment (start 154.7648 92.0242) (end 153.7742 92.0242) (width 0.4) (layer "F.Cu") (net 13) (tstamp c10f70c7-0334-4b37-8b18-0c0583785612))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 139.8375 103.8203) (end 139.8375 101.487) (width 0.4) (layer "F.Cu") (net 13) (tstamp c4577c96-68fc-42a1-9570-9e0407923c8b))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 143.8656 95.1504) (end 144.2192 95.504) (width 0.25) (layer "F.Cu") (net 13) (tstamp cbae47af-4887-48e4-95c7-332939c2c0c9))
(segment (start 153.7742 92.9386) (end 153.7742 92.0242) (width 0.4) (layer "F.Cu") (net 13) (tstamp e43f2464-2c37-4a8e-acf3-502234ab6cb3))
(segment (start 155.0924 92.3518) (end 154.7648 92.0242) (width 0.4) (layer "F.Cu") (net 13) (tstamp e97a64df-bd60-4788-831e-5a08d1bdc459))
(segment (start 150.3172 95.25) (end 150.876 94.6912) (width 0.3) (layer "F.Cu") (net 13) (tstamp f0db30d6-c20f-400f-806a-efdcba9e49c9))
(segment (start 145.81 89.2425) (end 145.81 88.533) (width 0.25) (layer "F.Cu") (net 13) (tstamp f2fdd02d-60f4-4943-ad08-ab1c1cc9d3a4))
(via (at 139.8375 101.487) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 13) (tstamp 989fd409-a9fc-46da-b3f8-d7648d9b5859))
(via (at 153.7742 92.9386) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 13) (tstamp a9a3da5f-0736-41ac-839b-969673b3ce17))
(via (at 140.7668 91.7448) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 13) (tstamp d13f8010-107c-418a-9ce3-b15d64ec7230))
(via (at 143.8656 94.5896) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 13) (tstamp fabefb4a-b29e-48f8-9e61-b592b2f0bf26))
(segment (start 140.7668 93.6244) (end 140.7668 91.7448) (width 0.4) (layer "B.Cu") (net 13) (tstamp 1af14add-a7f4-4caa-8aeb-c4c28fa4131c))
(segment (start 139.8375 101.487) (end 153.4265 101.487) (width 0.4) (layer "B.Cu") (net 13) (tstamp 4470c0ec-dd0c-4562-bd92-7c551dc688c1))
(segment (start 153.4265 101.487) (end 153.8075 101.106) (width 0.4) (layer "B.Cu") (net 13) (tstamp a0ec0a6f-7f4f-481a-a107-6c0573cf5200))
(segment (start 143.8656 94.5896) (end 141.732 94.5896) (width 0.4) (layer "B.Cu") (net 13) (tstamp b3048867-9b3b-45a0-81ef-1681e014bf48))
(segment (start 153.8075 101.106) (end 153.8075 92.9719) (width 0.4) (layer "B.Cu") (net 13) (tstamp d45e2231-657d-401f-92cc-39c15d30e931))
(segment (start 141.732 94.5896) (end 140.7668 93.6244) (width 0.4) (layer "B.Cu") (net 13) (tstamp e71988dc-694c-450b-879a-42df1c04558e))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 142.3924 93.728) (end 142.3924 97.2969) (width 0.25) (layer "F.Cu") (net 14) (tstamp 045371ec-edad-4d63-8b8f-40ed5e336bf3))
(segment (start 142.3924 97.2969) (end 143.4575 98.362) (width 0.25) (layer "F.Cu") (net 14) (tstamp 07bbcfe3-ac8d-4864-ba26-70995bdba010))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 145.81 93.7505) (end 142.4149 93.7505) (width 0.25) (layer "F.Cu") (net 14) (tstamp 672ba4e2-907b-4f91-aa0c-940560aa9cde))
(segment (start 154.0764 96.0628) (end 154.3792 95.76) (width 0.25) (layer "F.Cu") (net 15) (tstamp 0fde9e5a-781d-4cba-9702-d4d400a2d42d))
(segment (start 147.31 94.1175) (end 147.31 95.631492) (width 0.25) (layer "F.Cu") (net 15) (tstamp 2b07a606-1850-4c2c-88d2-e344f4d628c8))
(segment (start 155.0775 95.7749) (end 155.0924 95.76) (width 0.25) (layer "F.Cu") (net 15) (tstamp 42866959-c87e-4a43-847b-ffaf1fa99e67))
(segment (start 147.31 95.631492) (end 147.487508 95.809) (width 0.25) (layer "F.Cu") (net 15) (tstamp 6f7bae07-2595-459f-8495-ad3145404ee2))
(segment (start 151.328547 95.809) (end 151.377547 95.76) (width 0.25) (layer "F.Cu") (net 15) (tstamp 8d00b39b-6ec1-4f21-a98f-900d7d60d072))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 154.3172 98.362) (end 155.0924 97.5868) (width 0.25) (layer "F.Cu") (net 15) (tstamp acadb7f6-9c34-4546-92f0-01176976f6f2))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 154.3792 95.76) (end 155.0924 95.76) (width 0.25) (layer "F.Cu") (net 15) (tstamp bd2018f3-86ea-4333-a0b9-14b22289f22f))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(segment (start 153.4575 98.362) (end 154.3172 98.362) (width 0.25) (layer "F.Cu") (net 15) (tstamp d6fcc18c-504e-4dd9-9233-244b0efe70ec))
(segment (start 155.0924 97.5868) (end 155.0924 95.76) (width 0.25) (layer "F.Cu") (net 15) (tstamp d83d7fcb-f0ef-42eb-97f6-1951a01b3eb4))
New branch for new revision
2024-03-12 11:46:53 +01:00
(segment (start 151.582347 96.0628) (end 154.0764 96.0628) (width 0.25) (layer "F.Cu") (net 15) (tstamp eb3fd95a-31f6-4b59-9d7d-c7c78a9be90f))
(segment (start 151.328547 95.809) (end 151.582347 96.0628) (width 0.25) (layer "F.Cu") (net 15) (tstamp fc61e464-bb2b-476f-bfc1-d157cd7fe125))
(via (at 147.487508 95.809) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 15) (tstamp 20138616-1a75-489e-95db-a8ecb1a521b2))
(via (at 151.328547 95.809) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 15) (tstamp 22b8939d-7c9e-4dab-b0bd-bbc577d0c413))
(segment (start 147.487508 95.809) (end 151.328547 95.809) (width 0.25) (layer "B.Cu") (net 15) (tstamp ab2fecfc-1b54-49cd-b3a6-3514821fe977))
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(zone (net 13) (net_name "VDD") (layer "F.Cu") (tstamp 063147a2-001f-4131-b5fc-f635db00d88c) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30008)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
(polygon
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(filled_polygon
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(zone (net 13) (net_name "VDD") (layer "F.Cu") (tstamp 0de1dd3f-a791-4577-a257-3f3e70da811b) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30018)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
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(filled_polygon
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(zone (net 5) (net_name "SPI_MISO") (layer "F.Cu") (tstamp 0e97bd69-8a85-435e-a199-366a4b949daa) (name "$teardrop_padvia$") (hatch edge 0.5)
(priority 30002)
(attr (teardrop (type padvia)))
(connect_pads yes (clearance 0))
(min_thickness 0.0254) (filled_areas_thickness no)
(fill yes (thermal_gap 0.5) (thermal_bridge_width 0.5) (island_removal_mode 1) (island_area_min 10))
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(filled_polygon
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New branch for new revision
2024-03-12 11:46:53 +01:00
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
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New branch for new revision
2024-03-12 11:46:53 +01:00
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(xy 154.348775 95.383477)
(xy 154.334246 95.386809)
(xy 154.327599 95.387918)
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(xy 154.106385 95.501777)
(xy 153.957179 95.650982)
(xy 153.895859 95.684466)
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 152.19101 95.6873)
(xy 152.123971 95.667615)
(xy 152.104152 95.651796)
(xy 152.087697 95.635646)
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(xy 151.795017 95.349545)
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(xy 151.772323 95.333091)
(xy 151.753576 95.316483)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 151.700787 95.269717)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 151.700779 95.269713)
(xy 151.700778 95.269712)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 151.68591 95.261908)
(xy 151.635699 95.213323)
(xy 151.619725 95.145304)
(xy 151.643061 95.079446)
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(xy 151.812527 94.930666)
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)
)
(filled_polygon
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 144.581303 95.000924)
(xy 144.540893 94.981168)
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New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 144.501837 94.746418)
(xy 144.520878 94.5896)
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(xy 144.449192 94.29397)
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)
)
(filled_polygon
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 153.2983 90.381522)
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New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 153.2183 91.234339)
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 153.234103 91.32984)
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New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 153.3237 91.959468)
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 153.3237 92.045696)
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New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 153.118922 92.938599)
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(xy 153.137962 93.095418)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 153.188488 93.228643)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 153.19398 93.243123)
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 154.6419 94.13506)
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New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 154.283382 94.07779)
(xy 154.263942 94.05835)
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 151.528986 93.553249)
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New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 152.016215 93.5637)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 152.029639 93.5637)
(xy 152.043592 93.564488)
(xy 152.053456 93.565605)
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New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 152.174185 93.5637)
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(xy 152.46744 93.452483)
(xy 152.585683 93.34773)
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 152.746312 92.878885)
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New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 152.67542 92.608677)
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 151.722964 92.373914)
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New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 151.468371 92.578037)
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 151.41679 92.603372)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 151.410375 92.607953)
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 151.188581 92.83158)
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New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 150.89718 93.122981)
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 149.340139 90.865403)
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New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 149.3155 90.918243)
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 148.68138 93.307531)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 148.679499 93.29324)
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(xy 147.507595 88.218138)
(xy 147.454759 88.1935)
(xy 147.409188 88.187501)
(xy 147.409185 88.1875)
(xy 147.409179 88.1875)
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(xy 146.954759 88.1935)
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(xy 146.3345 88.1875)
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 146.2105 87.964165)
(xy 146.217511 87.923061)
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(xy 146.27444 87.820428)
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(xy 146.448072 87.7757)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 148.8105 87.7757)
)
)
(filled_polygon
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 143.07426 93.375)
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New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 142.895476 93.070102)
(xy 142.895478 93.070099)
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(xy 142.951982 92.461482)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 142.95037 92.458185)
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New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 143.3781 92.1953)
)
)
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 145.167134 87.77789)
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New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 145.4095 88.907024)
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 144.465139 90.865403)
(xy 144.456578 90.883764)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 144.4405 90.918243)
(xy 144.434501 90.963811)
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 144.434501 91.463811)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 144.4345 91.463821)
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 143.906513 91.522002)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 143.904552 91.517005)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 143.838129 91.433715)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 143.819879 91.41083)
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
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New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 141.2173 88.782365)
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 145.143932 87.7757)
New branch for new revision
2024-03-12 11:46:53 +01:00
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
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New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 140.473737 101.643818)
(xy 140.492778 101.487)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 140.473737 101.330182)
(xy 140.459465 101.292551)
(xy 140.440199 101.241749)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 140.41772 101.182477)
(xy 140.327983 101.05247)
(xy 140.20974 100.947717)
(xy 140.209738 100.947716)
(xy 140.209737 100.947715)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 140.069865 100.874303)
(xy 139.916486 100.8365)
(xy 139.916485 100.8365)
(xy 139.758515 100.8365)
(xy 139.758514 100.8365)
(xy 139.605134 100.874303)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 139.465262 100.947715)
(xy 139.347016 101.052471)
(xy 139.257281 101.182475)
(xy 139.25728 101.182476)
(xy 139.201262 101.330181)
(xy 139.182222 101.486999)
(xy 139.182222 101.487)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 137.7084 101.487)
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(xy 142.86199 94.18571)
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(xy 143.019429 94.131816)
(xy 143.056961 94.126)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 143.166065 94.126)
(xy 143.233104 94.145685)
(xy 143.278859 94.198489)
(xy 143.288803 94.267647)
(xy 143.282007 94.293971)
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(xy 143.210322 94.589599)
(xy 143.210322 94.5896)
(xy 143.229362 94.746418)
(xy 143.28538 94.894123)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 143.285381 94.894124)
(xy 143.375118 95.024132)
(xy 143.37755 95.026877)
(xy 143.387316 95.039443)
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(xy 143.555774 95.371611)
(xy 143.555775 95.371612)
(xy 143.555776 95.371614)
(xy 143.560329 95.377991)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 143.565178 95.384221)
(xy 143.565181 95.384226)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 143.582247 95.399936)
(xy 143.595661 95.412285)
(xy 143.628067 95.460744)
(xy 143.689477 95.627861)
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(xy 143.6987 95.675019)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 143.6987 95.725582)
(xy 143.709618 95.800518)
(xy 143.709618 95.800519)
(xy 143.709619 95.800521)
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(xy 144.281263 96.377181)
(xy 144.262222 96.533999)
(xy 144.262222 96.534)
(xy 144.281262 96.690818)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 144.332795 96.826696)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 144.33728 96.838523)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 144.427017 96.96853)
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(xy 150.932823 97.1805)
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(xy 150.208 97.406326)
(xy 150.208 97.406323)
(xy 150.207999 97.406321)
(xy 150.193467 97.333264)
(xy 150.193466 97.33326)
(xy 150.16533 97.291151)
(xy 150.138101 97.250399)
(xy 150.062099 97.199617)
(xy 150.055239 97.195033)
(xy 150.055235 97.195032)
(xy 149.982177 97.1805)
(xy 149.982174 97.1805)
(xy 148.9371 97.1805)
(xy 148.870061 97.160815)
(xy 148.824306 97.108011)
(xy 148.8131 97.0565)
(xy 148.8131 95.78559)
(xy 148.815739 95.760145)
(xy 148.816731 95.755413)
(xy 148.817967 95.749518)
(xy 148.814052 95.718111)
(xy 148.8131 95.702773)
(xy 148.8131 95.702676)
(xy 148.813099 95.702664)
(xy 148.810061 95.684466)
(xy 148.809676 95.682156)
(xy 148.808939 95.677102)
(xy 148.808679 95.675019)
(xy 148.802465 95.625161)
(xy 148.800217 95.617614)
(xy 148.797666 95.61018)
(xy 148.797665 95.610178)
(xy 148.797665 95.610177)
(xy 148.785515 95.587726)
(xy 148.770921 95.5194)
(xy 148.795584 95.454028)
(xy 148.851674 95.412367)
(xy 148.921384 95.407645)
(xy 148.982252 95.44103)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 149.02011 95.478888)
(xy 149.036235 95.498744)
(xy 149.038217 95.501777)
(xy 149.042176 95.507836)
(xy 149.067153 95.527276)
(xy 149.078678 95.537456)
(xy 149.078744 95.537522)
(xy 149.095657 95.549597)
(xy 149.099769 95.552662)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 149.111646 95.561906)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 149.141071 95.584809)
(xy 149.141073 95.584809)
(xy 149.14798 95.588547)
(xy 149.155058 95.592008)
(xy 149.155061 95.59201)
(xy 149.205245 95.60695)
(xy 149.210038 95.608485)
(xy 149.2596 95.6255)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 149.259603 95.6255)
(xy 149.26648 95.627861)
(xy 149.281457 95.632056)
(xy 149.584341 95.753367)
(xy 149.588283 95.754429)
(xy 149.59193 95.755413)
(xy 149.615951 95.764655)
(xy 149.618622 95.766016)
(xy 149.618629 95.766018)
(xy 149.646364 95.77041)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 149.710065 95.7805)
(xy 150.111534 95.780499)
(xy 150.111539 95.780499)
(xy 150.111539 95.780498)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 150.160595 95.772729)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 150.20297 95.766018)
(xy 150.202972 95.766017)
(xy 150.202975 95.766017)
(xy 150.313191 95.709859)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 150.344694 95.678354)
(xy 150.362896 95.66333)
(xy 150.368509 95.659534)
(xy 150.399646 95.644321)
(xy 150.401701 95.643654)
(xy 150.420615 95.639112)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 150.442504 95.635646)
(xy 150.462244 95.625586)
(xy 150.480211 95.618144)
(xy 150.50129 95.611296)
(xy 150.501299 95.611289)
(xy 150.502736 95.610558)
(xy 150.504687 95.610191)
(xy 150.510574 95.608279)
(xy 150.51082 95.609039)
(xy 150.571405 95.597657)
(xy 150.636147 95.62393)
(xy 150.676407 95.681033)
(xy 150.682134 95.735985)
(xy 150.673269 95.808999)
(xy 150.673269 95.809)
(xy 150.692309 95.965818)
(xy 150.736169 96.081465)
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(xy 150.838064 96.24353)
(xy 150.956307 96.348283)
(xy 150.956309 96.348284)
(xy 151.096181 96.421696)
(xy 151.249561 96.4595)
(xy 151.249562 96.4595)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 151.310996 96.4595)
(xy 151.331505 96.461207)
(xy 151.348279 96.464021)
(xy 152.027159 96.443526)
(xy 152.03733 96.441261)
(xy 152.064272 96.4383)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 154.024596 96.4383)
(xy 154.050041 96.440939)
(xy 154.053124 96.441585)
(xy 154.060668 96.443167)
(xy 154.092076 96.439251)
(xy 154.107414 96.4383)
(xy 154.107512 96.4383)
(xy 154.107514 96.4383)
(xy 154.128043 96.434873)
(xy 154.133073 96.434141)
(xy 154.185026 96.427666)
(xy 154.185028 96.427664)
(xy 154.192541 96.425428)
(xy 154.200006 96.422866)
(xy 154.200006 96.422865)
(xy 154.20001 96.422865)
(xy 154.246036 96.397957)
(xy 154.250593 96.395612)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 154.265502 96.388322)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 154.297611 96.372626)
(xy 154.297613 96.372623)
(xy 154.303994 96.368068)
(xy 154.310219 96.363222)
(xy 154.310226 96.363219)
(xy 154.345691 96.324692)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 154.349193 96.321042)
(xy 154.452402 96.217834)
(xy 154.513724 96.184351)
(xy 154.583416 96.189335)
(xy 154.584067 96.18958)
(xy 154.59543 96.193913)
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(xy 153.982177 100.431499)
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(xy 154.208 99.22867)
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(xy 154.231989 99.155364)
(xy 154.70491 98.51035)
(xy 154.704918 98.510333)
(xy 154.705441 98.509489)
(xy 154.706795 98.507777)
(xy 154.707812 98.506391)
(xy 154.707863 98.506428)
(xy 154.723244 98.486991)
(xy 155.321289 97.888946)
(xy 155.341146 97.872822)
(xy 155.350236 97.866884)
(xy 155.369671 97.841912)
(xy 155.379856 97.830381)
(xy 155.379856 97.83038)
(xy 155.379919 97.830318)
(xy 155.39203 97.813353)
(xy 155.395027 97.809334)
(xy 155.427209 97.767989)
(xy 155.427211 97.767981)
(xy 155.430947 97.761078)
(xy 155.434406 97.754003)
(xy 155.43441 97.753999)
(xy 155.449342 97.703841)
(xy 155.450886 97.699018)
(xy 155.4679 97.64946)
(xy 155.4679 97.649458)
(xy 155.467901 97.649456)
(xy 155.469191 97.641724)
(xy 155.470168 97.633886)
(xy 155.468006 97.581607)
(xy 155.4679 97.576483)
(xy 155.4679 96.396673)
(xy 155.480078 96.343083)
(xy 155.56809 96.159436)
(xy 155.592234 96.125344)
(xy 155.595473 96.122105)
(xy 155.595473 96.122104)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 155.595476 96.122102)
(xy 155.651982 96.006518)
(xy 155.6629 95.931582)
(xy 155.6629 95.588418)
(xy 155.651982 95.513482)
(xy 155.638897 95.486717)
(xy 155.595478 95.3979)
(xy 155.595476 95.397897)
(xy 155.53526 95.337681)
(xy 155.501775 95.276358)
(xy 155.506759 95.206666)
(xy 155.53526 95.162319)
(xy 155.595476 95.102102)
(xy 155.595478 95.102099)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 155.631065 95.029304)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 155.651982 94.986518)
(xy 155.6629 94.911582)
(xy 155.6629 94.568418)
(xy 155.651982 94.493482)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 155.623467 94.435155)
(xy 155.602324 94.391906)
(xy 155.592915 94.365395)
(xy 155.546091 94.16301)
(xy 155.5429 94.13506)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 155.5429 92.384061)
(xy 155.54368 92.370176)
(xy 155.54767 92.334766)
(xy 155.545034 92.320836)
(xy 155.537033 92.278553)
(xy 155.536264 92.274019)
(xy 155.527748 92.217515)
(xy 155.527748 92.217513)
(xy 155.527746 92.217509)
(xy 155.525236 92.209371)
(xy 155.522424 92.201334)
(xy 155.522423 92.201328)
(xy 155.495685 92.150741)
(xy 155.493623 92.146654)
(xy 155.468825 92.095158)
(xy 155.468823 92.095156)
(xy 155.468823 92.095155)
(xy 155.464042 92.088142)
(xy 155.458966 92.081265)
(xy 155.458965 92.081262)
(xy 155.418565 92.040862)
(xy 155.415347 92.037521)
(xy 155.37646 91.995609)
(xy 155.369192 91.989814)
(xy 155.369712 91.989161)
(xy 155.357467 91.979764)
(xy 155.106168 91.728465)
(xy 155.096902 91.718097)
(xy 155.088663 91.707766)
(xy 155.074679 91.69023)
(xy 155.074678 91.690229)
(xy 155.074677 91.690228)
(xy 155.04915 91.672824)
(xy 155.027433 91.658018)
(xy 155.023669 91.655347)
(xy 154.977686 91.621409)
(xy 154.970097 91.617398)
(xy 154.962475 91.613728)
(xy 154.907849 91.596879)
(xy 154.903444 91.59543)
(xy 154.849495 91.576552)
(xy 154.841126 91.574968)
(xy 154.832704 91.5737)
(xy 154.832702 91.5737)
(xy 154.775538 91.5737)
(xy 154.770901 91.573613)
(xy 154.768885 91.573537)
(xy 154.713789 91.571475)
(xy 154.704556 91.572516)
(xy 154.704462 91.571686)
(xy 154.689164 91.5737)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 154.3795 91.5737)
(xy 154.312461 91.554015)
(xy 154.266706 91.501211)
(xy 154.256535 91.433715)
(xy 154.281185 91.244093)
(xy 154.281184 91.244093)
(xy 154.281188 91.24407)
(xy 154.282951 91.197409)
(xy 154.282722 91.193152)
(xy 154.280609 91.17873)
(xy 154.279299 91.160754)
(xy 154.279299 90.832867)
(xy 154.278916 90.828002)
(xy 154.279167 90.827982)
(xy 154.278211 90.815202)
(xy 154.278272 90.80784)
(xy 154.212746 90.463821)
(xy 154.20149 90.404725)
(xy 154.1993 90.381524)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 154.1993 88.299861)
(xy 154.20008 88.285976)
(xy 154.200556 88.281757)
(xy 154.20407 88.250565)
(xy 154.193432 88.194341)
(xy 154.19267 88.189853)
(xy 154.184148 88.133313)
(xy 154.184147 88.133311)
(xy 154.184147 88.133309)
(xy 154.181629 88.125145)
(xy 154.178823 88.117124)
(xy 154.152106 88.066578)
(xy 154.150013 88.062433)
(xy 154.125225 88.010958)
(xy 154.12042 88.00391)
(xy 154.115367 87.997065)
(xy 154.115366 87.997062)
(xy 154.074952 87.956648)
(xy 154.071735 87.953308)
(xy 154.032857 87.911407)
(xy 154.02559 87.905612)
(xy 154.02611 87.904959)
(xy 154.01387 87.895566)
(xy 153.147768 87.029465)
(xy 153.138502 87.019097)
(xy 153.125068 87.002251)
(xy 153.116279 86.99123)
(xy 153.116278 86.991229)
(xy 153.116277 86.991228)
(xy 153.09075 86.973824)
(xy 153.069033 86.959018)
(xy 153.065269 86.956347)
(xy 153.019286 86.922409)
(xy 153.011697 86.918398)
(xy 153.004075 86.914728)
(xy 152.949449 86.897879)
(xy 152.945044 86.89643)
(xy 152.94146 86.895176)
(xy 152.933456 86.892375)
(xy 152.891095 86.877552)
(xy 152.882726 86.875968)
(xy 152.874304 86.8747)
(xy 152.874302 86.8747)
(xy 152.817138 86.8747)
(xy 152.812501 86.874613)
(xy 152.810485 86.874537)
(xy 152.755389 86.872475)
(xy 152.746156 86.873516)
(xy 152.746062 86.872686)
(xy 152.730764 86.8747)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 146.448068 86.8747)
(xy 146.424866 86.87251)
(xy 146.424297 86.872401)
(xy 146.424296 86.872401)
(xy 146.275894 86.844133)
(xy 146.139944 86.818238)
(xy 146.139929 86.818234)
(xy 146.021765 86.795727)
(xy 145.994752 86.793508)
(xy 145.967746 86.79129)
(xy 145.96774 86.79129)
(xy 145.967739 86.79129)
(xy 145.962822 86.791409)
(xy 145.962809 86.791409)
(xy 145.962808 86.79141)
(xy 145.962806 86.79141)
(xy 145.962796 86.791411)
(xy 145.945828 86.793642)
(xy 145.929667 86.7947)
(xy 145.595264 86.7947)
(xy 145.590409 86.795083)
(xy 145.590389 86.794836)
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(xy 145.350573 86.837567)
(xy 145.167702 86.8724)
(xy 145.167699 86.872401)
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(xy 145.143925 86.8747)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 142.018262 86.8747)
(xy 142.004379 86.87392)
(xy 141.99937 86.873355)
(xy 141.968963 86.869929)
(xy 141.91281 86.880554)
(xy 141.908241 86.881331)
(xy 141.851715 86.889851)
(xy 141.843532 86.892375)
(xy 141.835529 86.895176)
(xy 141.784985 86.921889)
(xy 141.780848 86.923977)
(xy 141.729358 86.948773)
(xy 141.722338 86.953559)
(xy 141.71546 86.958635)
(xy 141.675058 86.999037)
(xy 141.671722 87.002251)
(xy 141.629804 87.041146)
(xy 141.624013 87.048408)
(xy 141.623362 87.047888)
(xy 141.613967 87.060128)
(xy 140.471063 88.203032)
(xy 140.460698 88.212295)
(xy 140.432833 88.234517)
(xy 140.43283 88.234521)
(xy 140.400623 88.281757)
(xy 140.397944 88.285532)
(xy 140.364006 88.331518)
(xy 140.360016 88.339067)
(xy 140.356328 88.346725)
(xy 140.339473 88.401367)
(xy 140.338025 88.405768)
(xy 140.319153 88.459704)
(xy 140.317571 88.468059)
(xy 140.3163 88.4765)
(xy 140.3163 88.53366)
(xy 140.316213 88.538297)
(xy 140.314075 88.595409)
(xy 140.315116 88.604643)
(xy 140.314285 88.604736)
(xy 140.3163 88.620035)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 140.3163 90.876817)
(xy 140.312249 90.908254)
(xy 140.152676 91.517106)
(xy 140.152674 91.517117)
(xy 140.152662 91.517245)
(xy 140.152617 91.517435)
(xy 140.1518 91.522046)
(xy 140.151555 91.522002)
(xy 140.145161 91.549487)
(xy 140.130562 91.587982)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 140.111522 91.744799)
(xy 140.111522 91.7448)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 140.130562 91.901618)
(xy 140.182104 92.037521)
(xy 140.18658 92.049323)
(xy 140.276317 92.17933)
(xy 140.39456 92.284083)
(xy 140.394562 92.284084)
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(xy 140.687814 92.3953)
(xy 140.687815 92.3953)
(xy 140.845784 92.3953)
(xy 140.845785 92.3953)
(xy 140.986302 92.360665)
(xy 140.993066 92.359296)
(xy 140.994487 92.358923)
(xy 140.994496 92.358923)
(xy 141.603344 92.19935)
(xy 141.634781 92.1953)
(xy 141.764301 92.1953)
(xy 141.83134 92.214985)
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(xy 141.887039 92.336947)
(xy 141.875702 92.37376)
(xy 141.832818 92.46148)
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(xy 141.832818 92.954518)
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(xy 142.0169 97.0565)
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New branch for new revision
2024-03-12 11:46:53 +01:00
)
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(filled_polygon
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 157.092339 83.967185)
(xy 157.138094 84.019989)
(xy 157.1493 84.0715)
(xy 157.1493 108.1663)
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(xy 137.8324 108.2903)
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(xy 137.7084 101.487)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 139.182222 101.487)
(xy 139.201262 101.643818)
(xy 139.25728 101.791523)
(xy 139.347017 101.92153)
(xy 139.46526 102.026283)
(xy 139.465262 102.026284)
(xy 139.605134 102.099696)
(xy 139.758514 102.1375)
(xy 139.758515 102.1375)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 139.916484 102.1375)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 139.916485 102.1375)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 140.057002 102.102865)
(xy 140.063766 102.101496)
(xy 140.065187 102.101123)
(xy 140.065196 102.101123)
(xy 140.674044 101.94155)
(xy 140.705481 101.9375)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 153.394238 101.9375)
(xy 153.40812 101.938279)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 153.420921 101.939722)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 153.443533 101.94227)
(xy 153.443533 101.942269)
(xy 153.443535 101.94227)
(xy 153.499736 101.931635)
(xy 153.504226 101.930872)
(xy 153.560787 101.922348)
(xy 153.560791 101.922345)
(xy 153.568947 101.91983)
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(xy 153.57697 101.917023)
(xy 153.576972 101.917023)
(xy 153.627588 101.89027)
(xy 153.631593 101.888248)
(xy 153.683142 101.863425)
(xy 153.683143 101.863423)
(xy 153.683145 101.863423)
(xy 153.690195 101.858616)
(xy 153.697034 101.853567)
(xy 153.697038 101.853566)
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 154.258 93.795409)
(xy 154.260715 93.769601)
(xy 154.276037 93.697596)
(xy 154.391636 93.154348)
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(xy 154.391931 93.152959)
(xy 154.392604 93.149797)
(xy 154.392726 93.149823)
(xy 154.398639 93.126526)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 154.410437 93.095418)
(xy 154.429478 92.9386)
(xy 154.410437 92.781782)
(xy 154.35442 92.634077)
(xy 154.264683 92.50407)
(xy 154.14644 92.399317)
(xy 154.146438 92.399316)
(xy 154.146437 92.399315)
(xy 154.006565 92.325903)
(xy 153.853186 92.2881)
(xy 153.853185 92.2881)
(xy 153.695215 92.2881)
(xy 153.695214 92.2881)
(xy 153.541834 92.325903)
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(xy 153.193981 92.634075)
(xy 153.19398 92.634076)
(xy 153.137962 92.781781)
(xy 153.118922 92.938599)
(xy 153.118922 92.9386)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 153.137962 93.095414)
(xy 153.137964 93.095423)
(xy 153.156524 93.144361)
(xy 153.163826 93.17466)
(xy 153.164311 93.179038)
(xy 153.164312 93.179043)
(xy 153.164313 93.179045)
(xy 153.347947 93.758687)
(xy 153.35121 93.768985)
(xy 153.357 93.806435)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 153.357 100.868035)
(xy 153.337315 100.935074)
(xy 153.320681 100.955716)
(xy 153.276216 101.000181)
(xy 153.214893 101.033666)
(xy 153.188535 101.0365)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 140.705482 101.0365)
(xy 140.674045 101.032449)
(xy 140.666097 101.030366)
(xy 140.588613 101.010058)
(xy 140.06518 100.872872)
(xy 140.057221 100.871187)
(xy 140.044432 100.868035)
(xy 140.037358 100.866291)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 139.916486 100.8365)
(xy 139.916485 100.8365)
(xy 139.758515 100.8365)
(xy 139.758514 100.8365)
(xy 139.605134 100.874303)
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(xy 139.46526 100.947717)
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(xy 139.257281 101.182475)
(xy 139.25728 101.182476)
(xy 139.201262 101.330181)
(xy 139.182222 101.486999)
(xy 139.182222 101.487)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 137.7084 101.487)
(xy 137.7084 96.026)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 139.182222 96.026)
(xy 139.201262 96.182818)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 139.25728 96.330522)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 139.25728 96.330523)
(xy 139.347017 96.46053)
(xy 139.46526 96.565283)
(xy 139.465262 96.565284)
(xy 139.605134 96.638696)
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(xy 139.758515 96.6765)
(xy 139.916485 96.6765)
(xy 140.069865 96.638696)
(xy 140.20974 96.565283)
(xy 140.327983 96.46053)
(xy 140.41772 96.330523)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 140.430358 96.297197)
(xy 140.442977 96.27261)
(xy 140.447869 96.265239)
(xy 140.462548 96.229477)
(xy 140.568878 95.970416)
(xy 140.612543 95.915872)
(xy 140.678766 95.893594)
(xy 140.683591 95.8935)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 144.333974 95.8935)
(xy 144.401013 95.913185)
(xy 144.446768 95.965989)
(xy 144.456712 96.035147)
(xy 144.430424 96.092708)
(xy 144.431278 96.093297)
(xy 144.427961 96.098101)
(xy 144.427687 96.098703)
(xy 144.427027 96.099454)
(xy 144.337281 96.229475)
(xy 144.33728 96.229476)
(xy 144.281262 96.377181)
(xy 144.262222 96.533999)
(xy 144.262222 96.534)
(xy 144.281262 96.690818)
(xy 144.319718 96.792216)
(xy 144.33728 96.838523)
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(xy 144.54526 97.073283)
(xy 144.545262 97.073284)
(xy 144.685134 97.146696)
(xy 144.838514 97.1845)
(xy 144.838515 97.1845)
(xy 144.996485 97.1845)
(xy 145.149865 97.146696)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 145.149873 97.146691)
(xy 145.156887 97.144033)
(xy 145.156993 97.144313)
(xy 145.165852 97.140842)
(xy 145.165799 97.1407)
(xy 145.756213 96.917511)
(xy 145.800059 96.9095)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 151.622996 96.9095)
(xy 151.648441 96.912139)
(xy 151.651524 96.912785)
(xy 151.659068 96.914367)
(xy 151.690476 96.910451)
(xy 151.705814 96.9095)
(xy 151.705912 96.9095)
(xy 151.705914 96.9095)
(xy 151.726443 96.906073)
(xy 151.731473 96.905341)
(xy 151.783426 96.898866)
(xy 151.783428 96.898864)
(xy 151.790941 96.896628)
(xy 151.798406 96.894066)
(xy 151.798406 96.894065)
(xy 151.79841 96.894065)
(xy 151.844436 96.869157)
(xy 151.848993 96.866812)
(xy 151.863902 96.859522)
(xy 151.896011 96.843826)
(xy 151.896013 96.843823)
(xy 151.902394 96.839268)
(xy 151.90862 96.834421)
(xy 151.908626 96.834419)
(xy 151.944093 96.79589)
(xy 151.947595 96.79224)
(xy 152.324089 96.415746)
(xy 152.343946 96.399622)
(xy 152.353036 96.393684)
(xy 152.372471 96.368712)
(xy 152.382656 96.357181)
(xy 152.382656 96.35718)
(xy 152.382719 96.357118)
(xy 152.39483 96.340153)
(xy 152.397827 96.336134)
(xy 152.430009 96.294789)
(xy 152.430011 96.294781)
(xy 152.433747 96.287878)
(xy 152.437206 96.280803)
(xy 152.43721 96.280799)
(xy 152.452142 96.230641)
(xy 152.453686 96.225818)
(xy 152.4707 96.17626)
(xy 152.4707 96.176258)
(xy 152.470701 96.176256)
(xy 152.471991 96.168524)
(xy 152.472968 96.160686)
(xy 152.470806 96.108407)
(xy 152.4707 96.103283)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 152.4707 93.79576)
(xy 152.478711 93.751914)
(xy 152.536478 93.599099)
(xy 152.699745 93.167199)
(xy 152.702152 93.153459)
(xy 152.708347 93.1309)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 152.731437 93.070018)
(xy 152.750478 92.9132)
(xy 152.731437 92.756382)
(xy 152.67542 92.608677)
(xy 152.585683 92.47867)
(xy 152.46744 92.373917)
(xy 152.467438 92.373916)
(xy 152.467437 92.373915)
(xy 152.327565 92.300503)
(xy 152.174186 92.2627)
(xy 152.174185 92.2627)
(xy 152.016215 92.2627)
(xy 152.016214 92.2627)
(xy 151.862834 92.300503)
(xy 151.722962 92.373915)
(xy 151.604716 92.478671)
(xy 151.514981 92.608675)
(xy 151.51498 92.608676)
(xy 151.458962 92.756381)
(xy 151.439922 92.913199)
(xy 151.439922 92.9132)
Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
(xy 151.458962 93.070014)
(xy 151.458964 93.070023)
(xy 151.482252 93.131428)
(xy 151.488624 93.155017)
(xy 151.490654 93.1672)
(xy 151.692882 93.702165)
(xy 151.711689 93.751914)
(xy 151.7197 93.795761)
New branch for new revision
2024-03-12 11:46:53 +01:00
(xy 151.7197 95.077167)
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
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New branch for new revision
2024-03-12 11:46:53 +01:00
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
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New branch for new revision
2024-03-12 11:46:53 +01:00
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
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New branch for new revision
2024-03-12 11:46:53 +01:00
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
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New branch for new revision
2024-03-12 11:46:53 +01:00
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
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New branch for new revision
2024-03-12 11:46:53 +01:00
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
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New branch for new revision
2024-03-12 11:46:53 +01:00
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Sent to production - Replaced the header with a 2mm version. - Rewired to match the new header. - Reduced the width of the board. - Added teardrops to the tracks' endpoints. - Tested with thte DRC. - Generated productun files and sent them to JLCPCB.
2024-03-12 14:01:42 +01:00
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New branch for new revision
2024-03-12 11:46:53 +01:00
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